“…In the context of optimization for device performance enhancement in terms of LEE and output power, factors such as nanostructural composition, selection of metallic elements at reflection, barrier or adhesion, and wafer bonding layers need to be considered in correlation with electrical resistivity, coefficient of thermal expansion (CTE) or mechanical stress, fabrication methodology, and grain morphological parameters. On the basis of our analysis and results, possible optimization suggestions are given as follows: - GB engineering, that is, grain structure, SB (TBs), and texture orientation need to be well-controlled as electron or photon scattering mechanism and electromigration lifetime are highly dependent on the grain size distribution. ,,
- Nanotwinned metals, for example, Ag, should be promoted as these structures exhibit distinctive properties (e.g., high tensile strength, good ductility, thermal stability, and electrical conductivity) as compared to the nanocrystalline or ultrafine-grained metals. ,
- To mitigate issues of Ag diffusion into the GaN or active region and In/Ga out-diffusion into the Ag mirror layer, high thermal treatments should be avoided on Ag and p-GaN layers to prevent metal–semiconductor diffusions. , Ni/Ag/TiW metal stack is found to tolerate high-temperature annealing
- To reduce thermal stress between GaN and metal–alloy-based interfaces, the tunable incorporation of diamond-like carbon (DLC) layers on the reflective layer has the distinct capability to match its CTE with GaN and hence enhances the thermal diffusion. ,
- The GaN/Ag interface needs diffusion barrier layers such as tin–zinc oxide (TZO) and nickel–titanium (NiTi)-related alloys that can effectively block Ag diffusion .
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