1994
DOI: 10.1109/55.289480
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Improved prediction of interface-trap generation in NMOST's

Abstract: Absfract-Hot-carrier-induced interface-trap generation in NMOSFET's is a serious reliability hazard for CMOS circuits. Its prediction has been either inaccurate or it needed. many process dependent fitting parameters. We introduce a new method that improves lifetime prediction by orders of magnitude. Our method requires no additional fitting parameter and is applicable in existing circuit simulators. From the (time dependent) voltages and currents, available in a circuit simulator, we predict the number of gen… Show more

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Cited by 9 publications
(6 citation statements)
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“…Using the lifetime model given by Eq. (2) as proposed in [4], with one technology-related constant Cw and universal coefficients a and b, we are able to predict rlc0, (shown in Figure 3).…”
Section: Model For Interface States Creation Includingmentioning
confidence: 81%
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“…Using the lifetime model given by Eq. (2) as proposed in [4], with one technology-related constant Cw and universal coefficients a and b, we are able to predict rlc0, (shown in Figure 3).…”
Section: Model For Interface States Creation Includingmentioning
confidence: 81%
“…Most of this work relied on empirical degradation modeling, using curve fitting to a simple power law to describe the MOSFET parameters' time dependence [1,2]. Some attempts were made to model the actual (physical) damage mechanisms involved [2,3,4]. Focus has been on modeling interface states creation, since NMOSFET hot-carrier degradation is governed by this mechanism.…”
Section: Introductionmentioning
confidence: 99%
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“…This has been reported before. 6 Hu et al suggest, when presenting the Berkeley model,' that degradation is fastest at the &(max) condition. A contradiction thus exists which suggests that, although confidence in reliability predictions at Ib(max) is high,l the model was not well verified at…”
Section: Prediction Plotmentioning
confidence: 99%
“…(2) as proposed in [4], with one technology-related constant Cw and universal coefficients a and b, we are able to predict rlc0, (shown in Figure 3). (2) where Is, IB, are source and substrate currents respectively, W is transistor width and q~ox=3.2eV, $i= 1.3eV, Eox=(Vc-VT-VD)/tox, E0=80MV/m, a= 11, b=0.5.…”
Section: Model For Interface States Creation Includingmentioning
confidence: 89%