Comprehensive physical modeling of nmosfet hot-carrier-induced degradation

Lunenborg, M.M.; Graaff, H.C. de; Mouthaan, A.J.; Verweij, J.F.

doi:10.1016/0026-2714(96)00170-9

Cited by 3 publications

(2 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In the circuits in this paper, the electric fields are limited using circuit techniques. For verification purposes during the design of the circuits, extensive reliability simulations [18], [19] were performed. Lifetime measurements under accelerated stress conditions on realized I/O circuits confirm the simulated data.…”

Section: Lifetime Issuesmentioning

confidence: 99%

“…With large drain-source voltages and transistors operating in saturation, carriers flowing from source to drain may gain high energies, i.e., become hot, close to the drain region. Upon collisions with the silicon lattice, a small fraction of these hot carriers shoot into the gate oxide near the drain area, thereby slowly degrading the gate oxide and the transistor's performance [3], [4], [18]. This so-called hot-carrier degradation effect depends among others on the transistor's length and its biasing conditions:…”

Section: B Hot-carrier Degradationmentioning

confidence: 99%

See 1 more Smart Citation

5.5-V I/O in a 2.5-V 0.25-μm CMOS technology

Annema

Geelen

Jong

2001

IEEE J. Solid-State Circuits

111

View full text Add to dashboard Cite

A robust high-voltage-tolerant I/O that does not need process options is presented, demonstrated on 5.5-V-tolerant I/O in a 2.5-V 0.25-m CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation. Measurements on realized circuits, under accelerated stress conditions, indicate an extrapolated lifetime of hundreds of years for 5.5-V pad voltage swing, 2.2-V supply voltage. The shown concepts can easily be scaled toward newer processes or other interfacing voltages.

show abstract

Section: Lifetime Issuesmentioning

confidence: 99%

Section: B Hot-carrier Degradationmentioning

confidence: 99%

5.5-V I/O in a 2.5-V 0.25-μm CMOS technology

Annema

Geelen

Jong

2001

IEEE J. Solid-State Circuits

111

View full text Add to dashboard Cite

show abstract

Drain breakdown in submicron MOSFETs: a review

Wong

2000

Microelectronics Reliability

View full text Add to dashboard Cite

Modeling kinetics of gate oxide reliability using stretched exponents

Krishnan

Koldyaev

2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320)

View full text Add to dashboard Cite

the pure logarithmic model can fit the pure exponential model well initially as In this work, we propose a novel approach to modeling the kinetics of gate transition starts, it cannot match the pure exponent in the tail, since the oxide reliability, using the stretched-exponential form. We show how the logarithmic model abruptly decays. Conversely, the longer the tail, which is dispersive nature of characteristic times pertaining to kinetic transitions the case as degradation proceeds with multiple mechanisms, greater is the during oxide degradation, are very well captured by stretched-exponential difference between the logarithmic model (represented by eqn. 4, shown in functions. The use of the stretched exponents to model oxide reliability is Fig.2: log-model), and the actual kinetics. demonstrated with two real examples. Modeling kinetics of reliability IntroductionHere we demonstrate the applicability of the stretched exponent to modelThe qualification of oxide lifetime in product often requires compact models multiple stages of HCI and NBTl without having to changer the functional to predict the impact of oxide degradation at the device and circuit level. In form itself. First, HCI stressing of an NMOS device (Lpoly=O.35um) was the past, several functional forms of degradation describing the kinetics of performed and BSlM parameters were extracted at several stress intervals.degradation have been proposed. Here, we present a unifying alternative-Details of the experiment and extractions can be seen in Ref. 6. As shown the stretched exponential model, which lends more insight into the physics in Fig, 3, for the first 2 decades of stressing, the reverse short channel effect of degradation and also is advantageous from a compact modeling (RSCE) parameter degrades, corresponding to an increase in Vt. Once this standpoint. The stretched exponent as described in eqn. 1 (see table$ I), is mechanism has saturated, degradation of short channel effect (SCE) often used to characterize relaxation in disordered systems [l]. In a regular parameter begins and lasts till the end of stressing. The kinetics of NMOS system, relaxation process ' I e transport kinetics, is governed by a HCI degradation therefore proceeds in two stages: First, characterized by characteristic time, z, and can be modeled by a regular (pure) exponent. In RSCE degradation (single pure exponent process), followed by SCE disordered systems, there may be two or more competing mechanisms degradation (second stage also a pure exponent process). We speculate each with its own z, and sometimes, a single mechanism may have z which that the first mechanism is one of electron trapping and interface state is statistically distributed [2]. Thus, the stretched exponent has been used generation in the spacer edge. The second stage is that of electron trapping previously to model the kinetics in disordered system mainly to capture this and interface state generation in the channel. After prolonged stressing, distribution of 2. Here, we extend this principle to mode...

show abstract

Comprehensive physical modeling of nmosfet hot-carrier-induced degradation

Cited by 3 publications

References 7 publications

5.5-V I/O in a 2.5-V 0.25-μm CMOS technology

5.5-V I/O in a 2.5-V 0.25-μm CMOS technology

Drain breakdown in submicron MOSFETs: a review

Modeling kinetics of gate oxide reliability using stretched exponents

Contact Info

Product

Resources

About