5.5-V I/O in a 2.5-V 0.25-μm CMOS technology

Annema, Anne-Johan; Geelen, Govert; Jong, P.C. de

doi:10.1109/4.910493

Cited by 111 publications

(47 citation statements)

References 19 publications

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“…The most common way to extend the tolerable supply voltage using low-voltage CMOS technology is to use the cascode or stacked transistor structure [77], [78], which in combination with thick-oxide transistors allows operation at higher supply voltage while keeping reliability at a high level. The result is higher output power, higher load, and lower current, which potentially leads to lower losses and higher efficiency.…”

Section: Circuit Solutionsmentioning

confidence: 99%

A Review of Watt-Level CMOS RF Power Amplifiers

Johansson

Fritzin

2014

IEEE Trans. Microwave Theory Techn.

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Abstract-This paper reviews the design of watt-level integrated CMOS RF power amplifiers (PAs) and state-of-the-art results in the literature. To reach watt-level output power from a single-chip CMOS PA, two main strategies can be identified: use of high supply voltage, and use of matching and power combination. High supply voltage limits are closely related to device design in the fabrication process. However, the maximum operating voltage can be improved by amplifier class selection, circuit solutions, and process modifications or mask changes. High output power can also be reached by the use of on-chip matching and power combination, commonly using on-chip transformers. Reliability often sets the limits for the PA design, and PA degradation mechanisms are reviewed. A compilation of state-of-the-art published results for linear and switched wattlevel PAs, as well as a few fully integrated CMOS PAs, is presented and discussed.

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Section: Circuit Solutionsmentioning

confidence: 99%

A Review of Watt-Level CMOS RF Power Amplifiers

Johansson

Fritzin

2014

IEEE Trans. Microwave Theory Techn.

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“…3b) [10]. While this implementation is more reliable, the speed is limited by the three series transistor stack and feedback tracking loops.…”

Section: Mqwm Transmittermentioning

confidence: 99%

High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects

Palermo¹,

Horowitz²

2006

2006 Proceedings of the 32nd European Solid-State Circuits Conference

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Abstract-Small, high-speed and low power optical transmitter circuits are needed for optical interconnects to play a role in improving chip I/O bandwidth. This paper demonstrates two different transmitter designs fabricated in a 1V 90nm CMOS technology, one suitable for driving vertical cavity surface emitting lasers (VCSELs) and the other for driving multiple quantum well modulators (MQWMs). A four-tap current summing FIR equalizer extends VCSEL data rate for a given average current. It consumes 80mW at 18Gb/s operation and occupies 0.03mm 2 area. The MQWM transmitter has a pulsedcascode output stage capable of supplying a voltage swing of twice the 1V supply without overstressing thin-oxide core devices. It consumes 38mW at 16Gb/s and occupies 0.014mm 2 area.

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“…To solve the gate-oxide reliability issue without using the additional thick gate oxide process (also known as dual gate oxides in some CMOS processes [5], [6]), the stacked-MOS configuration has been widely used in the mixed-voltage I/O buffers [7]- [12], and in the power-rail ESD clamp circuits [13]. The typical 3-V/5-V-tolerant mixed-voltage I/O circuit is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%