Improved reversed nested miller frequency compensation technique based on current comparator for three-stage amplifiers

Zaherfekr, Mehdi; Biabanifard, Ali

doi:10.1007/s10470-019-01405-1

Cited by 25 publications

(13 citation statements)

References 31 publications

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“…Both of them are more efficient regarding GBW, while they have more circuit complexity. In addition, a more complex frequency compensation network in the current mode is presented in [12]. This work describes the method as a transfer function (TF) similar to others and verifies theoretical findings via computer simulations.…”

Section: Introductionsupporting

confidence: 55%

Four‐stage CMOS amplifier: frequency compensated using differential block

Daryan

Khalesi

Ghods

2020

IET Circuits, Devices & Systems

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Section: Introductionsupporting

confidence: 55%

Four‐stage CMOS amplifier: frequency compensated using differential block

Daryan

Khalesi

Ghods

2020

IET Circuits, Devices & Systems

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“…Similarly, several three-and four-stage amplifiers have been reported with different stability, speed, and design complexity. [7][8][9][10][11][12][13][14][15][16][17][18][19][20] The operating principle of these amplifiers is the same and requires that the Miller capacitor is placed in loops with negative gain to ensure proper Miller effect.…”

Section: Introductionmentioning

confidence: 99%

“…This is because the compensation capacitors have to be placed on high‐impedance nodes. Similarly, several three‐ and four‐stage amplifiers have been reported with different stability, speed, and design complexity 7–20 . The operating principle of these amplifiers is the same and requires that the Miller capacitor is placed in loops with negative gain to ensure proper Miller effect.…”

Section: Introductionmentioning

confidence: 99%

Three‐stage CMOSamplifier: Frequency compensated using fully differential block

Bandari

Setoudeh

Tavakoli

et al. 2022

Int J Numerical Modelling

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The advancement of CMOS technology limits designers' options for multi‐stage configurations as a promising alternative to cascade structures. The main issue of designing multi‐stage amplifiers is frequency compensation since cascade structures are volatile. An efficient three‐stage amplifier, which is frequency compensated using a fully differential block, is proposed in this work. The differential block enhances the Miller effect to reduce the size of compensation capacitors, and this leads to less die occupation. The compensation network shares the differential block between two Miller loops while two Miller capacitors at the outputs of the differential block cause pole‐zero cancelation to increase operating frequency range. The proposed structure is modeled by a linear transfer function and simulated via HSPICE software using 0.180.25emμm0.25em CMOS library. Simulation results indicate excellent performance and acceptable robustness against parameter mismatches and probable fabrication errors. According to the simulations, the proposed amplifier has a DC gain of 1050.25emdB, a gain‐bandwidth product of 4.80.25emMHz, a phase margin of 72°, and a power dissipation of 3600.25emμW. The high performance of the proposed three‐stage amplifier with an enhanced figure of merit makes it a perfect alternative to the amplifiers based on the conventional reverse nested Miller compensation.

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“…For example, for one parameter in some sentences the maximum range is set, whereas for the same parameter in other sentences the minimum value is set. Since many of the same parameters are repeated in different polynomial sentences, this problem is quite significant 14‐17 . The result is that very few sentences are omitted, although the simplified equation is valid over a broader range.…”

Section: Introductionmentioning

confidence: 99%

Four‐stage CMOS amplifier design based on symbolic calculations: Stack comparison approach

Bahadoran

Reza-Alikhani

2021

Int J Numerical Modelling

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This paper presents a simple simplification method to design a multistage amplifier. The simplification procedure is based on a defined criterion which mainly related to ignoring negligible terms. In order to verify the validity and accuracy of the exploited method, a complex four‐stage CMOS amplifier is considered. Simplified transfer function and circuit simulator output are compared. According to simulation results obtained from HSPICE circuit simulator and TSMC 0.18 μm CMOS technology, the proposed approach expresses a bitter performance by 1% error. The aim is to propose a preprocessing algorithm. This helps main algorithm to deal with simpler inputs. In this way, a preprocessing algorithm is investigated which reduces CPU time and needed memory to simplify heavy symbolical transfer functions. Since target is analog and mix mode circuit, some circuit‐based assumptions are considered.

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Improved reversed nested miller frequency compensation technique based on current comparator for three-stage amplifiers

Cited by 25 publications

References 31 publications

Four‐stage CMOS amplifier: frequency compensated using differential block

Four‐stage CMOS amplifier: frequency compensated using differential block

Three‐stage CMOSamplifier: Frequency compensated using fully differential block

Four‐stage CMOS amplifier design based on symbolic calculations: Stack comparison approach

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