“…ESD stress causes large electric fields and high current densities, resulting in breakdown of the oxide of CMOS and thermal damage [4,5,6,7]. ESD protection in high-speed ICs becomes more challenging than others because it requests low parasitic capacitance, low leakage current and almost zero series resistance [8,9,10]. To address this, dual-diode based ESD protection circuits, often named "rail-based" ESD protection circuits [11], are widely implemented for radio-frequency (RF), digital and high-speed interface ICs [12,13,14,15,16,17,18,19,20,21].…”