Improved target impedance and IC transient current measurement for power distribution network design

Kim, Jingook; Wu, Songping; Wang, Hanfeng; Takita, Yuzou; Takeuchi, Hayato; Araki, Kiyomichi; Feng, Gang; Fan, Jun

doi:10.1109/isemc.2010.5711316

Cited by 23 publications

(4 citation statements)

References 3 publications

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“…With the maximum switching current, the PCB PDN system will generate the maximum voltage ripple. The maximum tolerable PDN input impedance which is corresponded to the maximum tolerable ripple voltage is known as target impedance [7]. The input impedance of the PDN is compared to target impedance to evaluate the design performance.…”

Section: Introductionmentioning

confidence: 99%

Analytical PDN voltage ripple calculation using simplified equivalent circuit model of PCB PDN

Zhao

Huang

Shringarpure

et al. 2015

2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity

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Printed circuit board (PCB) power distribution network (PDN) design performance depends on the peak voltage ripple caused by the integrated circuit (IC) switching currents. The input impedance seen by the IC looking into the PCB PDN can be calculated using a physics-based circuit model extracted from the cavity model approach. The input impedance is fitted to a simplified circuit model used to represent the PCB PDN. Using a switching current profile, the frequency domain noise voltage is found and transformed to the time domain ripple waveform which can then be used to evaluate the PDN design performance.

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Section: Introductionmentioning

confidence: 99%

Analytical PDN voltage ripple calculation using simplified equivalent circuit model of PCB PDN

Zhao

Huang

Shringarpure

et al. 2015

2015 IEEE Symposium on Electromagnetic Compatibility and Signal Integrity

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show abstract

“…The input impedance of the PDN is compared to a defined target impedance to evaluate the design performance [2], [3]. Target impedance can be thought of as the impedance profile which will create the max tolerable noise voltage, at the IC pins for a particular IC current draw.…”

Section: Introductionmentioning

confidence: 99%

“…(a) High layer count stack up and top view of a PCB-PDN with many decaps placed on the top layer around the IC, bottom of the IC and on the bottom layer but away from the IC, (b) A generic (asymptotic) response for a PCB-PDN, with target impedance as defines in[3].…”

mentioning

confidence: 99%

On finding the optimal number of decoupling capacitors by minimizing the equivalent inductance of the PCB PDN

Shringarpure

Zhao

Wei

et al. 2014

2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)

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PCB-PDN design remains a challenge with the reducing noise margins. One aspect of PDN design is finding the number of decoupling capacitors required for each power rail. As more capacitors are added, the mid frequency equivalent inductance in the impedance of the PCB-PDN converges to a minimum value for each placement pattern. This convergence is studied for different placement patterns to find the least number of capacitors required to satisfy a certain convergence criteria. A first principle method is used resonant cavity model for the analysis.

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“…The analysis of the impedance, loop inductance and parasitic parameters of power distribution network (PDN) is the key for solving power integrity problems. The analysis of PDN is based on the input impedance observed by the integrated circuit (IC) looking into the PDN, and the performance of PDN is evaluated by comparing the input impedance with the target impedance [1,2].…”

Section: Introductionmentioning

confidence: 99%

The Analysis and Experimental Investigation of Electromagnetic Characteristics on High Speed Circuit PDN With Multislots

Li¹,

Gao²,

Zuo³

et al. 2018

PIER M

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Abstract-The electromagnetic characteristics of a high speed IC power distribution network (PDN) are of vital important with the rapid increasing of operation speed and scale down CMOS manufacturing size, in particular, the fundamental electromagnetic theory including impedance and loop inductance of various designed IC power-plane structures. In addition, the area occupancy ratio of slot (AOROS) of irregular parallel-plane structures with multi-slots plays a key role in PDN impedance and loop inductance, where the influence of AOROS on impedance and loop inductance is investigated for various structures. Moreover, experimental work is carried out to validate the influence of AOROS on impedance and loop inductance of the PDN. The simulation and measurement of impedance are performed up to 10 GHz, and a good agreement is obtained between the simulation and experiment.

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Improved target impedance and IC transient current measurement for power distribution network design

Cited by 23 publications

References 3 publications

Analytical PDN voltage ripple calculation using simplified equivalent circuit model of PCB PDN

Analytical PDN voltage ripple calculation using simplified equivalent circuit model of PCB PDN

On finding the optimal number of decoupling capacitors by minimizing the equivalent inductance of the PCB PDN

The Analysis and Experimental Investigation of Electromagnetic Characteristics on High Speed Circuit PDN With Multislots

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