On finding the optimal number of decoupling capacitors by minimizing the equivalent inductance of the PCB PDN

Abstract

PCB-PDN design remains a challenge with the reducing noise margins. One aspect of PDN design is finding the number of decoupling capacitors required for each power rail. As more capacitors are added, the mid frequency equivalent inductance in the impedance of the PCB-PDN converges to a minimum value for each placement pattern. This convergence is studied for different placement patterns to find the least number of capacitors required to satisfy a certain convergence criteria. A first principle method is used resonant cavity model for the analysis.

Efficient Iterative Process Based on an Improved Genetic Algorithm for Decoupling Capacitor Placement at Board Level

“…Moreover, the resulting optimization offers a distribution of the decap close to the four ports, due to the shorter distance and, as a consequence, the corresponding lower "mounting" inductance associated with the loop between the integrated circuit (IC) power port and the decap. Although this distribution could be expected by the well-known impact of "local" decoupling strategies [16,22], the developed tool, together to the DF simulator, is able to obey to the physics of this problem, thus, relieving the designer from a trial-based PDN decoupling.…”

“…However, the use of decoupling capacitances (decaps) [12] is still one of the more effective and currently investigated. The current trend in the PDN decoupling for voltage noise reduction is the optimized placement of decoupling capacitors, with the key task aimed at minimizing their number (and thus, the inherent costs) and at achieving the most effective PDN impedance design [13][14][15][16][17][18][19][20][21][22]. The goal of the PDN design is to achieve the input impedance seen by the power pins of the active devices (integrated circuits, IC, such as FPGA, DSP etc.)…”

Analytical PDN voltage ripple calculation using simplified equivalent circuit model of PCB PDN

“…Before CPlane gets shorted, current path starts from the IC to the decoupling capacitors, passes through the power planes, and returns back to the IC. The equivalent inductance for this current path is called LEQ [9]. After CPlane is effectively shorted, the current can only reach the plane cavity, pass through the power planes, and then return back to the IC.…”

“…After CPlane is effectively shorted, the current can only reach the plane cavity, pass through the power planes, and then return back to the IC. The equivalent inductance for this path is called IC connection inductance LIC [9].…”