Improved VHDL Input for High-Level Synthesis Tool xTractor

Ellervee, Peeter; Ivask, E.; Kruus, Margus

doi:10.1109/bec.2006.311067

Cited by 3 publications

(2 citation statements)

References 4 publications

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“…Assumptions, supported constructs, and translation principles are described below in brief. Details are presented in the description of the improved VHDL translator [13].…”

Section: Behavioral Vhdl Construct Translationmentioning

confidence: 99%

Translating behavioral VHDL for emulation

2007

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Emulation is widely used to increase simulation speed. The main problem is that to map it into hardware, the description of the model must be synthesizable. This is not difficult for modules described at lower abstraction levels but almost impossible for behavioral descriptions when using traditional synthesis approaches. In this paper, an overview is given how to use behavioral synthesis principles to convert behavioral VHDL constructs into synthesizable ones. Differences between translation for synthesis and emulation are outlined.

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“…Assumptions, supported constructs, and translation principles are described below in brief. Details are presented in the description of the improved VHDL translator [13].…”

Section: Behavioral Vhdl Construct Translationmentioning

confidence: 99%

Translating behavioral VHDL for emulation

2007

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“…First, the behavioral description of the target digital systems is converted to an intermediate representation using a compiler (Corre, Senn, Julien, & Martin, 2004). This intermediate representation (i.e., Data Flow Graph in our case) is given to the tool as an input along with design constraints (Ellervee, Ivask, & Kruus, 2006). The constraints currently considered by our tool include performance, area, memory space consumption, power/energy utilization, and reliability.…”

Section: High Level Synthesismentioning

confidence: 99%

Ayse

Ozturk

Karaagac

Koc

2014

International Journal of Technology and Educational Marketing

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This paper presents an educational Electronic Design Automation tool called AYSE (Automated SYstem Synthesis Environment). AYSE is developed to help undergraduate and graduate students better understand and implement fundamental concepts in digital electronic design and synthesis courses. It receives an intermediate format that represents the system behavior and a set of constraints as input; and generates the representation of the actual circuit using the electronic components (functional units, memory and steering logic components) available in its technology library. A user can load the input from an external file or utilize the graphical user interface (GUI). Similarly, the output can be displayed using GUI or written to a file. The user is able to interact with the tool during the synthesis process and select the algorithms to perform three main synthesis tasks; namely, resource allocation, operation scheduling and resource binding/sharing. It is also possible to run the tool for the most efficient solution. The effectiveness of the tool was tested in a graduate level course.

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An Educational Tool for Digital Electronic System Synthesis and Optimization

Koc

Ozturk

Advances in Educational Marketing, Administration, and Leadership

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Considering the complexity of today's digital electronic systems, it is crucial to have open-source electronic design automation (EDA) tools specifically developed for educational purposes. Such tools can easily be modified to meet the demands of the course being taught and they can be configured to expose the intermediate steps during the design process. This chapter presents an educational EDA tool to help students better understand and implement fundamental concepts in digital electronic design and synthesis courses. The tool receives an intermediate format that represents the target system behavior and a set of constraints as input, and generates the representation of the actual circuit using high-level electronic components such as functional units, memory, and steering logic components available in its technology library. It considers execution delay, area, memory space consumption, and reliability constraints. The user is able to interact with the tool during the design process and select the algorithms to perform various synthesis and optimization tasks.

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Improved VHDL Input for High-Level Synthesis Tool xTractor

Cited by 3 publications

References 4 publications

Translating behavioral VHDL for emulation

Translating behavioral VHDL for emulation

Ayse

An Educational Tool for Digital Electronic System Synthesis and Optimization

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