This paper offers an Internet-based environment for enhancing problem-specific design flows with test pattern generation and fault simulation capabilities. Automatic Test Pattern Generation (ATPG) and fault simulation tools at structural and hierarchical levels available at geographically different places running under the virtual environment using the MOSCITO system are presented. These tools can be used separately, or in multiple applications, for test pattern generation of digital circuits. In order to link different tools together and with commercial design systems, respectively a set of translators was developed. The functionality of the integrated design and test system was verified by several benchmark circuits
In this paper, an improved version of VHDL compiler for an academic high-level synthesis tool xTractor is presented. A synthesizable subset of behavioral VHDL, accepted by the compiler, is described in brief. Improvements that allow descriptions at higher abstraction level are outlined. The compiler translates the behavioral VHDL subset into control oriented flow-chart like internal description IRSYD. The mapping of higher abstraction level VHDL constructs into IRSYD is described in more details. A short description of the synthesis tool is presented.
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