Improved weight assignment for logic switching activity during at-speed test pattern generation

Wu, Mengfan; Pan, Heng‐Chih; Wang, T.-H.; Huang, Jiun-Lang; Tsai, Kun-Han; Cheng, Wu-Tung

doi:10.1109/aspdac.2010.5419834

Cited by 27 publications

(12 citation statements)

References 16 publications

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“…Although WSA lacks accuracy in PSN estimation, it is widely used to approximate PSN due to its low computation complexity. Many approaches have been proposed to enhance the accuracy of WSA-based PSN estimation by incorporating either spatial or temporal information, or both [14].…”

Section: Psn Estimationmentioning

confidence: 99%

Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise

2014

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Timing prediction has become more and more difficult with shrinking technology nodes. Combining the presilicon delay model with post-silicon timing measurements has the potential to improve the accuracy of timing analysis. In this work, we address the problem of automatic test pattern generation for understanding circuit timing sensitivity to power supply noise (PSN) during post-silicon validation. Long paths are selected from a pseudo functional test set to span the power delivery network. To determine the sensitivity of timing to onchip noise, the patterns are intelligently filled to achieve the desired PSN level. Our previous PSN control scheme is enhanced to consider both spatial and temporal information for better correlation with functional PSN. These patterns can be used to understand timing sensitivity in post-silicon validation by repeatedly applying the path delay test while sweeping the PSN experienced by the path from low to high.

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Section: Psn Estimationmentioning

confidence: 99%

Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise

2014

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“…Substituting (5) into (9), we get that (10) However, according to [12] the computation of the bits si can be transformed as follows:…”

Section: Kogge-stone Addersmentioning

confidence: 99%

Implementation of Error Detection Network in High- Speed Variable Latency Speculative Han-Carlson Adder

2016

IJSR

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Variable latency adders have been recently proposed in literature. In variable latency adder unwanted interconnections also reduced compared with kogge-stone topology. Kogge-Stone adder consists of large number of black cells and many wire tracks. A variable latency adder employs speculation: the exact arithmetic function is replaced with an approximated one that is faster and gives the correct result most of the time, but not always. In order to detecting the error, error detection network also used. The approximated adder is augmented with an error detection network that asserts an error signal when speculation fails. Speculative variable latency adders to reduce average delay compared to traditional architectures. This paper proposes a novel variable latency speculative adder based on Han-Carlson parallel-prefix topology which proposes the error detection network that reduces error probability compared to previous approaches. Several variable latency speculative adders, for various operand lengths, using both Han-Carlson and KoggeStone topology, have been synthesized using Xilinx 14.3. Obtained results show that proposed variable latency Han-Carlson adder used in high-speed application.

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“…Prior work [10] has focused on vetoing compactions that would exceed a noise limit, but have not looked at compacting patterns to minimize critical patterns. Furthermore, we will investigate more accurate and efficient PSN estimation methods, such as [24] and apply the proposed scheme to multiple clock domains. …”

Section: E Compacted Pattern Considerationmentioning

confidence: 99%