2017
DOI: 10.1109/led.2017.2736000
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Improvement in Device Performance of Vertical Thin-Film Transistors Using Atomic Layer Deposited IGZO Channel and Polyimide Spacer

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Cited by 60 publications
(39 citation statements)
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“…IGZO film could also be deposited by ALD. [62] ALD has an advantage of conformal deposition, but the process is slow and difficult to vary the chemical composition. Besides, solutionprocessed IGZO has potential to reach lower cost than vacuum deposition methods, [63] but it still requires a high-temperature (>350 C) or photochemical activation (e.g., deep-ultraviolet irradiation) process [64] to achieve a stable and dense solid structure with reasonable electrical performance and operating stability.…”
Section: Igzo Channel Layermentioning
confidence: 99%
“…IGZO film could also be deposited by ALD. [62] ALD has an advantage of conformal deposition, but the process is slow and difficult to vary the chemical composition. Besides, solutionprocessed IGZO has potential to reach lower cost than vacuum deposition methods, [63] but it still requires a high-temperature (>350 C) or photochemical activation (e.g., deep-ultraviolet irradiation) process [64] to achieve a stable and dense solid structure with reasonable electrical performance and operating stability.…”
Section: Igzo Channel Layermentioning
confidence: 99%
“…In most cases this has taken the form of solution processing methods such as spin coating, inkjet printing, or spray pyrolysis [137][138][139][140] . There is also a growing body of work using spatial atomic layer deposition (S-ALD) that began in 2015 with work from Illiberi et al 141 and has expanded to several research groups in the last few years [142][143][144][145] . in large area and roll-to-roll processing, it remains very much a developing area with significant challenges, and is partially reviewed in the recent work from Sheng et al 145 .…”
Section: Deposition Techniques For A-igzomentioning
confidence: 99%
“…This design has come to attention as the push for reduced device footprint has forced researchers to consider alternatives to planar geometries 5 . Here the channel is defined by the thickness of a device layer, commonly an additional dielectric layer as in figure 5h) 143,[178][179][180][181] , although the channel can also be defined by the thickness of the gate or the semiconductor itself [182][183][184][185] . This approach is currently very new and only a small amount of work on it exisists.…”
Section: Vertical Tftsmentioning
confidence: 99%
“…Since the first report on indium-gallium-zinc oxide thin-film transistors (TFTs) by Nomura et al in 2004, oxide semiconductor TFTs have drawn significant attention owing to their high electrical performance, low fabrication temperature, and superior large area uniformity [ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 ]. To date, a variety of oxide semiconductors have been developed to enhance the electrical performance and stability of oxide TFTs [ 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 ]. However, fabricating p-channel oxide TFTs consisting of electrical performance comparable to that of n-channel oxide TFTs remain a challenge.…”
Section: Introductionmentioning
confidence: 99%