Improvement of Data Retention in Floating Gate Flash EEPROM’s with P-Doped Floating Gate

Abstract

Data retention capability is the key to design a highly reliable non-volatile memory cell. We demonstrated in our previous work [1] that the use of p-type floating gate(FG), instead of the commonly used n-type doped FG in an n-channel cell, is feasible for high speed performance as well as better endurance. In this paper, a p-doped floating gate on both n-and p-channel flash cells can be achieved with superior data retention characteristics. Since the p-floating gate cell exhibits a larger tunnel oxide field and a smaller electric field across the ONO dielectric during programming, the p-type FG cell shows much better charge loss behavior as compared to n-type FG ones. Results have been demonstrated for both n-and p-channel flash cells. Along with the high speed, better disturb, and good endurance advantages, the p-type FG cell is very promising for high performance and high reliability applications.

The split-gate flash memory with an extra select gate for automotive applications

“…However, the higher erase voltage also worsens the post cycling punch through disturb (PTD) and program wordline disturb (PWD) due to the higher channel leakage caused by the wordline oxide degradation [4,5]. Stack gate flush with a p-type-floating gate (FG) and used the drain-side program of channel hot electron injection [6,7] was found could also speed programming and had a better retention. Similarly, program efficiency in a split-gate flash with a p-floating gate could be higher as the source-side injection was used [8] due to the change of work function in floating gate poly.…”