No abstract

No abstract

Data retention capability is the key to design a highly reliable non-volatile memory cell. We demonstrated in our previous work [1] that the use of p-type floating gate(FG), instead of the commonly used n-type doped FG in an n-channel cell, is feasible for high speed performance as well as better endurance. In this paper, a p-doped floating gate on both n-and p-channel flash cells can be achieved with superior data retention characteristics. Since the p-floating gate cell exhibits a larger tunnel oxide field and a smaller electric field across the ONO dielectric during programming, the p-type FG cell shows much better charge loss behavior as compared to n-type FG ones. Results have been demonstrated for both n-and p-channel flash cells. Along with the high speed, better disturb, and good endurance advantages, the p-type FG cell is very promising for high performance and high reliability applications.

Due to the superior error correction performance, Turbo Code has become one of the best choices to deal with errors induced from high-noise communication channels. Nevertheless, to achieve such a superior performance, it needs to repeat a probabilistic decoding operation over each corrupted data block for several times and thus exhibits considerable decoding latency. A decoding latency as such may forbid possible cost reduction on designing a communication receiver, especially when a strict round-trip latency is specified. This paper proposed a Turbo Decoding scheme which benefits from the diversity characteristic provisioned by some communication systems, and thus is able to efficiently reduce required decoding latency thereof. To verify the performance, the popular Max-Log-MAP algorithm has been cascaded with the proposed scheme and is simulated with a range of AWGN conditions. Possible alternatives to the proposed scheme are also presented while the trends of the resource utilization and the BER performance are presented and discussed. As the experimental result shows, the proposed Turbo decoding schemes can introduce at least 4x latency reduction comparing to the traditional scheme, while preserving an adequate decoding performance.

To lower the risk in developing a TCP/IP OffloadEmbedded System (TOES), one may rely on certain platform containing a single or plurality of embedded microprocessor(s). However, previous work shows that it is not easy to use such a slow-clocked microprocessor(s) to achieve high speed goal. Hence this work proposed an efficient architecture of a TOES as well as buffering processes which guarantee a deterministic response time of allocating host buffers during data transmitting and receiving. The experimental results show that the proposed system achieves 859.86 Mbps in receiving and 789.41 Mbps in transmitting, and meanwhile, saves about 1/2 to 3/4 host CPU power compared with the one using conventional TCP/IP stack.