Improvement of Electrical Properties of MOCVD HfO[sub 2] by Multistep Deposition

Abstract

A multistep metallorganic chemical vapor deposition ͑MOCVD͒ technique of HfO 2 gate dielectric and its electrical properties are reported. This technique involves steps of ''deposition followed by postdeposition annealing'' of HfO 2 in which each step is repeated on the previously deposited and annealed HfO 2 . Our experiment demonstrates significant reduction of gate leakage current after high-temperature annealing for HfO 2 deposited using a multistep deposition technique as compared to conventional single-step deposition. This improvement is attributed to offset of the grain boundaries and pinholes from one layer to another in a multistep deposited HfO 2 which eventually leads to blockage of leakage current path.A key challenge in meeting the requirement of The International Technology Roadmap for Semiconductors ͑ITRS͒ for highly scaled low standby power devices is to have low gate leakage current. A report shows that a gate oxide thickness of 10-12 Å could serve as the practical limit for reducing SiO 2 thickness. 1 It is then clear that a gate dielectric with a permittivity higher than that of SiO 2 is required to meet the low standby power application requirement. Toward this end, HfO 2 has drawn significant attention as an alternative to SiO 2 due to its high dielectric permittivity and reasonable barrier height. Reduction of gate leakage current by orders of magnitudes has been demonstrated by HfO 2 , 2 but successful integration of HfO 2 into the conventional complementary metal oxide semiconductor ͑CMOS͒ process remains a challenge due to its thermal instability. 3 Study has shown that HfO 2 crystallizes at a moderately low annealing temperature, 3 forming grain boundaries that may act as a leakage current path as well as a diffusion path for impurities such as O 2 and B. In addition, there have been difficulties in the metallorganic chemical vapor deposition ͑MOCVD͒ process such as carbon contamination. The effect of carbon incorporation into the high-k film on electrical properties has not been studied in detailed but initial results indicate desorption of CuO bonds at high temperature which in turn lead to pinhole formation that causes high leakage current. 4 In this study, we reduced the leakage current by blocking the direct leakage current path caused by grain boundaries and pinholes through a multistep deposition process. The final gate stack consists of multilayers HfO 2 with each layer deposited and annealed independently in a cluster tool so as to offset the grain boundaries and pinholes from one layer to another. ExperimentalThe fabrication of metal-oxide-silicon ͑MOS͒ capacitors started with field oxide isolation on p-type Si͑100͒ substrate ͑4-8 ⍀ cm resistivity͒ and active region patterning. After the standard pregate cleaning process with a final dilute 1% HF dip, the wafers were inserted into a three-chamber MOCVD cluster tool. For some wafers, surface nitridation was conducted at 700°C in an NH 3 ambient prior to HfO 2 deposition. HfO 2 was deposited using Hf(OC(CH 3 ) 3 ) 4 ͓Hf 't-butox...

Identifying Performance-Critical Defects in the High-k/Metal Gate Stacks

“…RSCE appears to be stronger in the modified, double-layer ALD film (Curve M, Figure 4) prepared by the deposition of half of a target dielectric thickness, followed by a post-deposition anneal (PDA), second deposition, and a final PDA (the double-layer dielectric has the same EOT and physical thickness as the conventional single-layer film). The double-layer film with an intermediate anneal was expected to prevent propagation of voids across the total film thickness and improve film leakage current (6). Apparently more effective contaminant ion diffusion in the double-layer film is attributed to the presence of an internal interface in the bulk of the film.…”

Nanoscale characterization of advanced high-?? gate dielectric stacks via scanning tunneling microscopy

“…for as long as 60 s. Upon the completion of the first PDA, an additional 1 nm layer of HfSiO x was deposited, followed by a second PDA under the same conditions. Because of the densification of the film during the first PDA [80,106], several extra ALD cycles were added to the second deposition step in order to match the final physical thickness of the control sample, which was prepared in a single D&A step.…”

“…4.8), indicating a severe GB degradation. A huge negative-I t increase implies that the ultrathin IL beneath a GB is highly susceptible to trap generation as [80] and Yeo et al [106] reported that a high-κ dielectric deposited and annealed in multiple steps was denser than that achieved via a single step. The improvement was attributed to a more efficient removal of impurity (the most common being carbon originated from the precursor used for the atomic layer deposition (ALD) process) from a thinner high-κ film, as was verified by Nabatame et al [78].…”

“…Lee et al[70] reported no increase in the IL thickness for a 4.5 nm HfO 2 subjected to 700 C annealing in N 2 for as long as 60 s. Upon the completion of the first PDA, another 1 nm layer of HfSiO x was deposited, followed by a second PDA under the same condition (labeled as HfSiO(2-step)). Due to the densification of the film during the first PDA[80,106], additional ALD cycles were introduced in the second D&A step in order to achieve the identical total physical thickness as the control sample, which was prepared in a single D&A step (labeled as HfSiO(1-step)). In order to ensure that the STM-measured results are directly relevant to an actual fully-processed gate stack, TiN (corresponds to the gate electrode) was sputter-deposited on the HfSiO x film and the wafer was subsequently subjected to a 1000 C spike anneal in N 2 (corresponds to the source/drain dopant activation).…”

Failure mechanisms in HfO2 high-k gate stack MOSFETs

“…Also different annealing conditions have been proposed for better performance of the HfO 2 gate stack devices[74,75,80]. Bera et al[99] reported that multistep metallorganic chemical vapor deposition (MOCVD) of HfO 2 can suppress the gate leakage current due to the offset of the grain boundaries and the pinholes from one layer to another.On the other hand, the reliability study of HfO 2 gate dielectric is getting more attention by the researchers. McPherson et al[100][101][102] reported that the ultimate breakdown strength (E bd ) of a dielectric material decreases with increasing κ and having a relationship of E bd proportional to κ -1/2 .…”