High-resolution x-ray photoelectron spectroscopy (XPS) was applied to characterize the electronic structures for a series of high-k materials (HfO2)x(Al2O3)1−x grown on (100) Si substrate with different HfO2 mole fraction x. Al 2p, Hf 4f, O 1s core levels spectra, valence band spectra, and O 1s energy loss all show continuous changes with x in (HfO2)x(Al2O3)1−x. These data are used to estimate the energy gap (Eg) for (HfO2)x(Al2O3)1−x, the valence band offset (ΔEν) and the conduction band offset (ΔEc) between (HfO2)x(Al2O3)1−x and the (100) Si substrate. Our XPS results demonstrate that the values of Eg, ΔEν, and ΔEc for (HfO2)x(Al2O3)1−x change linearly with x.

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A multistep metallorganic chemical vapor deposition ͑MOCVD͒ technique of HfO 2 gate dielectric and its electrical properties are reported. This technique involves steps of ''deposition followed by postdeposition annealing'' of HfO 2 in which each step is repeated on the previously deposited and annealed HfO 2 . Our experiment demonstrates significant reduction of gate leakage current after high-temperature annealing for HfO 2 deposited using a multistep deposition technique as compared to conventional single-step deposition. This improvement is attributed to offset of the grain boundaries and pinholes from one layer to another in a multistep deposited HfO 2 which eventually leads to blockage of leakage current path.A key challenge in meeting the requirement of The International Technology Roadmap for Semiconductors ͑ITRS͒ for highly scaled low standby power devices is to have low gate leakage current. A report shows that a gate oxide thickness of 10-12 Å could serve as the practical limit for reducing SiO 2 thickness. 1 It is then clear that a gate dielectric with a permittivity higher than that of SiO 2 is required to meet the low standby power application requirement. Toward this end, HfO 2 has drawn significant attention as an alternative to SiO 2 due to its high dielectric permittivity and reasonable barrier height. Reduction of gate leakage current by orders of magnitudes has been demonstrated by HfO 2 , 2 but successful integration of HfO 2 into the conventional complementary metal oxide semiconductor ͑CMOS͒ process remains a challenge due to its thermal instability. 3 Study has shown that HfO 2 crystallizes at a moderately low annealing temperature, 3 forming grain boundaries that may act as a leakage current path as well as a diffusion path for impurities such as O 2 and B. In addition, there have been difficulties in the metallorganic chemical vapor deposition ͑MOCVD͒ process such as carbon contamination. The effect of carbon incorporation into the high-k film on electrical properties has not been studied in detailed but initial results indicate desorption of CuO bonds at high temperature which in turn lead to pinhole formation that causes high leakage current. 4 In this study, we reduced the leakage current by blocking the direct leakage current path caused by grain boundaries and pinholes through a multistep deposition process. The final gate stack consists of multilayers HfO 2 with each layer deposited and annealed independently in a cluster tool so as to offset the grain boundaries and pinholes from one layer to another. ExperimentalThe fabrication of metal-oxide-silicon ͑MOS͒ capacitors started with field oxide isolation on p-type Si͑100͒ substrate ͑4-8 ⍀ cm resistivity͒ and active region patterning. After the standard pregate cleaning process with a final dilute 1% HF dip, the wafers were inserted into a three-chamber MOCVD cluster tool. For some wafers, surface nitridation was conducted at 700°C in an NH 3 ambient prior to HfO 2 deposition. HfO 2 was deposited using Hf(OC(CH 3 ) 3 ) 4 ͓Hf 't-butox...

We demonstrate enhancement of electron mobility in nMOSFET using an ultrathin pure Ge crystal channel layer directly grown on a bulk Si wafer. A thin Si crystal layer is also grown on top of a Ge crystal channel layer as a capping layer. Using the Si/Ge/Si structure, a maximum 2.2X enhancement in electron mobility is achieved while good gate dielectric properties and junction qualities of bulk Si devices are maintained.

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