Improvement of SiN_x:H/InP gate structures for the fabrication of metal insulator semiconductor field-effect transistors

Abstract

In this paper we report on the optimization of the SiN x :H insulator, deposited by the electron cyclotron resonance (ECR) plasma method, as a dielectric for metal-insulator-semiconductor (MIS) structures built on an InP compound semiconductor. Two different MIS structures have been obtained in which the minimum of the interface trap density (D it,min) at the insulator/InP interface attains values of device quality. In the first structure, a Al/SiN 1.5 :H/SiN 1.6 :H/InP dual-layer insulator was obtained and optimized after rapid thermal annealing treatment at 500 • C for 30 s. After this treatment, the value of D it,min was 9 × 10 11 cm −2 eV −1. In the second structure, the MIS structure was Al/SiN 1.6 :H/InP single-layer insulator, in which the InP surface was exposed to an N 2 plasma prior to the SiN 1.6 :H film deposition. In this case, the value of D it,min was 1.6 × 10 12 cm −2 eV −1. Both types of structures were used as gate insulators on N-channel enhanced-mode MIS field-effect transistor test devices. From the dc output characteristics of the transistors, we obtain values for the electron channel mobility in the range 1550-1600 cm 2 V −1 s −1. This is a confirmation of the great potential of the ECR plasma method as a simple way to obtain device quality gate structures on InP without the use of passivation processes of the InP surface prior to the deposition of the gate dielectric, thus simplifying the whole device fabrication procedure.

High pressure sputtering as a viable technique for future high permittivity dielectric on III–V integration: GdOx on InP demonstration

“…Then, if the Fermi level becomes pinned while sweeping the traps, the measured C-V curve can be misinterpreted as a full inversion-depletion-accumulation sweep. 21 Our group previously reported results on SiN x deposited by ECR-CVD on InP with an optimal annealing temperature of 500 C. 27 Other groups kept the temperature at 300 C, 41 but longer annealing processes were used. 39 If this were the case in our samples, we would see a dramatic decrease of the capacitance at positive voltages with increasing measuring frequency.…”

Scavenging effect on plasma oxidized Gd2O3grown by high pressure sputtering on Si and InP substrates

“…The device sizes ranged from 50 × 50 to 700 × 700 μm 2 . Standard RCA (Radio Corporation of America) cleaning [26] was performed for Si samples, while InP substrates were cleaned with 10% diluted iodic acid for 1 min [27]. Before introducing the samples into the chamber, a 30 s HF dip was carried out in order to remove the native oxides.…”

(Invited) High Pressure Sputtering for High-K Dielectric Deposition. Is It Worth Trying

“…On the substrates used for MIS fabrication, square openings were defined on field oxide. The Si samples were cleaned by a standard RCA (Radio Corporation of America) process, while the InP substrates were prepared with a 1 min immersion in iodic acid diluted to 10% by weight (23). Just before the introduction to the HPS chamber both substrates were etched in a 1:50 HF solution for 30 s to remove the native oxides.…”