Improvement of SRAM-based failure analysis using calibrated Iddq testing

Balachandran, H.; Walker, D.M.H.

doi:10.1109/vtest.1996.510847

Cited by 17 publications

(10 citation statements)

References 24 publications

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“…The defect-to-bitmap mapping is then linked to specific defect types. Physical failure analysis is avoided, since the defect type is known based on electrical test data [67]- [69]. In finding the defect-to-bitmap mapping, Fig.…”

Section: Yield Modeling Based On Physical Failure Analysismentioning

confidence: 99%

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A Survey of Yield Modeling and Yield Enhancement Methods

Milor

2013

IEEE Trans. Semicond. Manufact.

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Section: Yield Modeling Based On Physical Failure Analysismentioning

confidence: 99%

“…Most bitmaps could be mapped to one or two defect types [68], [69]. When two or more defects map to the same bitmap signature, the probability of failure distribution among the defects depends on the defect density distribution among layers, which is not known a priori.…”

Section: Yield Modeling Based On Physical Failure Analysismentioning

confidence: 99%

A Survey of Yield Modeling and Yield Enhancement Methods

Milor

2013

IEEE Trans. Semicond. Manufact.

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“…But these detection processes are time consuming. Testing using quiescent current (IDDQ) is also used [5] [6]. However, some defects in SRAM cells may not be detected using IDDQ.…”

Section: Introductionmentioning

confidence: 99%

Detection of Faults in SRAM Using Transient Current Testing

A¹

2013

IOSRJVSP

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Fast development of memory devices cause more area occupation of memory in a chip and the strong market competition have increased the standards of the produced memories. The increased demand on reliability has, in turn, stressed the importance of failure analysis and device testing techniques. More and more effort and thought is being dedicated to the study of testing memory devices with regards to new fault models, fault diagnosis and new memory architectures. In order to detect these faults, March test has been widely used. However, some defects on SRAM cells may not be detected by the conventional March tests. This detection of defects in CMOS SRAM has been a time consuming process. Hence we go for current testing method. This paper implements a transient current testing (I DDT ) method to detect defects in CMOS SRAM cells. By monitoring a transient current pulse during a transition write operation or a read operation, defects can be detected. In order to measure the transient current pulse, a current monitoring circuit is designed.

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“…Since the quiescent current for a "good" CMOS circuit is very small, if an abnormally high IDDQ is detected for the DUT, it is determined to be faulty. Test techniques that monitor the IDDQ of CMOS circuits are effective to detect defects causing significant change in leakage [3,4,9,10,14]. For CMOS SRAM circuits, the defects which can be detected by IDDQ testing include most of the bridging defects which can be modeled as stuck-at fault (SAF) e.g.…”

Section: Iddq Testing For Drg-cachementioning

confidence: 99%

“…IDDQ testing has been established as an effective technique [3,4,6,7,9,10] to test CMOS SRAMs for realizing highly reliable systems. IDDQ testing is based on determining the quiescent supply current and can be used for burn-in elimination and for identifying issues related to yield and reliability [6,14,15].…”

Section: Introductionmentioning

confidence: 99%

A high performance IDDQ testable cache for scaled CMOS technologies

Bhunia

Roy

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

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Quiescent supply current (IDDQ) testing is a useful test method for static CMOS RAM and can be combined with functional testing to reduce total test time and to increase reliability. However the sensitivity of IDDQ testing deteriorates significantly with technology scaling as intrinsic leakage of CMOS circuits increases. In this paper, we use a design technique for high-performance cache, which greatly improves leakage current and hence the IDDQ testability of the cache with technology scaling. We utilize the concept of Gated-Ground [1, 2] (NMOS transistor inserted between ground line and SRAM cell) to achieve reduction in leakage energy due to stacking effect of transistor without significantly affecting performance. Simulation results for a 64K cache shows 20% average improvement in IDDQ sensitivity for TSMC 0.25µm technology, while the improvement is more than 1000% for 70nm predictive technology model [12].

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Improvement of SRAM-based failure analysis using calibrated Iddq testing

Cited by 17 publications

References 24 publications

A Survey of Yield Modeling and Yield Enhancement Methods

A Survey of Yield Modeling and Yield Enhancement Methods

Detection of Faults in SRAM Using Transient Current Testing

A high performance IDDQ testable cache for scaled CMOS technologies

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