Improving Branch Prediction and Predicated Execution in Out-of-Order Processors

Abstract

If-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-predict branches, transforming control dependencies into data dependencies. Although it is globally beneficial, it has a negative side-effect because the removal of branches eliminates useful correlation information necessary for conventional branch predictors. The remaining branches may become harder to predict. However; in predicated ISAs with a compare-branch model, the correlation information not only resides in branches, but also in compare instructions that compute their guarding predicates. When a branch is removed, its correlation information is still available in its compare instruction.We propose a branch prediction scheme based on predicate prediction. It has three advantages: First, since the prediction is not done on a branch basis but on a predicate define basis, branch removal after if-conversion does not lose any correlation information, so accuracy is not degraded. Second, the mechanism we propose permits using the computed value ofthe branch predicate when available, instead of the predicted value, thus effectively achieving 100% accuracy on such early-resolved branches. Third, as shown in previous work, the selective predicate prediction is a very effective technique to implement if-conversion on outof-order processors, since it avoids the problem of multiple register definitions and reduces the unnecessary resource consumption ofnullified instructions. Hence, our approach enables a very efficient implementation of if-conversion for an out-of-order processor; with almost no additional hardware cost, because the same hardware is used to predict the predicates of if-converted code and to predict branches without accuracy degradation.

Early Register Release for Out-of-Order Processors with RegisterWindows

“…The register stack engine have been replaced by our scheme. The microarchitec- ture features predicate prediction [17]. Load-store queues, as well as the data and control speculation mechanisms defined in IA64, are also modeled and integrated in the memory disambiguation subsystem.…”

How to implement effective prediction and forwarding for fusable dynamic multicore architectures

“…The predicate prediction mechanisms in the literature [4,16,13] only focus on lightly predicated code, in which dependent chains of predicates do not exist. IPP proposed in this paper, conversely, performs both branch and predicate prediction across large and heavily predicated hyperblocks, where chains of dependent predicates exist.…”

“…Unlike out-of-order designs that use predicates to avoid hard-topredict branches [4,16], EDGE architectures employ predicates to build large instruction blocks to reduce fetch bottlenecks. The combination of speculative block-based execution and predication within blocks in EDGE architectures moves branch prediction off of the critical path and alleviates the fetch bandwidth bottleneck.…”

Role of Multiblocks in Control Flow Prediction using Parallel Register Sharing Architecture

“…This leads to a nearly optimal performance speedup of 2% of ideal speedup. A compilation framework [1] is presented that allows a compiler to maximize the benefits of prediction. Steve Carr (1996) [15] shown how the weakness of traditional heuristics are exploited.…”

“…It has been observed that ILP is greatly forced by branch instructions. Also it has been observed that branch prediction is employed with speculative execution [1]. However, inevitable branch misprediction compromises such a remedy.…”