Improving bulk FinFET DC performance in comparison to SOI FinFET

Poljak, Mirko; Jovanović, Vladimir; Suligoj, Tomislav

doi:10.1016/j.mee.2009.01.066

Cited by 49 publications

(18 citation statements)

References 16 publications

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“…Negative value indicates opposite behavior. The Bulk FinFET having shallower source/drain junction than bottom of gate (negative ∆X) shows better performance than normal Bulk FinFET (∆X=0) as reported in [15]. Table 3 shows that the subthreshold performance is improved with negative value of misalignment ∆X.…”

Section: Pie Gate Bulk Finfet With Punch Through Stoppermentioning

confidence: 83%

“…Punchthrough stopper [14] and Piegate bulk FinFET i.e. isolation oxide with source/drain-tobody (S/D) junctions shallower than gate at bottom [15] is reported as Fig 1. Here, Pie-gate structure (Fig 2) is basically represented by misalignment (ΔX j =negative) between the S/D junctions and the bottom of the gate electrode. Deeper gate electrode (shallower junctions) has an enhanced control over the bottom of the Fin and its electrostatic control also serves as a punch-thorough stopper which enhances the device subthreshold performance [15].…”

Section: Introductionmentioning

confidence: 99%

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Optimization of Pie-gate Bulk FinFET Structure

Tripathi¹,

Vadthiya²,

Mishra³

2012

IJCA

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In this paper we propose a novel Pie gate bulk FinFET structure for logic applications suitable for system-on-chip (SOC) requirements. The influence of gate at bottom to junction depth, misalignment was examined for deeper junctions and shallower junctions. It has shown that bulk FinFET with source/drain to body (S/D) junctions shallower than gate at bottom has equal or better subthreshold performance than SOI FinFET. Further, we extend the concept of heavy body doping in bulk FinFETs of Pie-gate structure. The characteristics of such bulk FinFET structure is analyzed by 3D device simulation and compared with SOI FinFET. General termsBulk Fin-shaped field-effect transistor (FinFET), shortchannel performance, SS, DIBL, sentaurus TCAD device simulator.

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Section: Pie Gate Bulk Finfet With Punch Through Stoppermentioning

confidence: 83%

Section: Introductionmentioning

confidence: 99%

Optimization of Pie-gate Bulk FinFET Structure

Tripathi¹,

Vadthiya²,

Mishra³

2012

IJCA

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“…A thick gate-tosubstrate isolation oxide also can prevent leakage [8]. The PTS with shallow S/D junction that can suppress leakage and suppress SCEs has also been proposed [9]. Though the thick gate-to-substrate isolation oxide is of use, the effective fin height is reduced as part of fin is surrounded by isolation oxide but not conducting current.…”

Section: Introductionmentioning

confidence: 99%

A pragmatic design methodology using proper isolation and doping for bulk FinFETs

Liao

Chiang

Lai

et al. 2013

Solid-State Electronics

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“…Giuseppe Iannaccone [9] has reported the relevance of CAD tools for understanding the physical mechanisms and performance evaluation and optimization of device structures which includes ballistic strained silicon MOSFETs and silicon nanowire transistors. Mirko Poljak et al [10] have reported the improvement in the dc performance of bulk FinFET in comparison with SOI FinFET by reducing the S/D junction depth. Jerry G. Fossum et al [11] has presented the results of the assessment of SOI and bulk FinFETs suggesting the viability of SOI FinFET.…”

Section: Introductionmentioning

confidence: 99%