Improving Characteristics of LUT-Based Moore FSMs

Abstract

Almost any digital system includes sequential blocks which can be represented using a model of finite state machine (FSM). It is very important to improve such characteristics of FSM circuits as the number of logic elements, operating frequency and consumed energy. The paper proposes a novel design method targeting a decrease in the number of look-up table (LUT) elements in logic circuits of FPGA-based Moore FSMs. The method is based on using two sets of variables for encoding the collections of outputs. It results in a partition of the set of outputs by two blocks. The outputs from the first block depend on state variables, the outputs from the second block on additional variables. A method is proposed for splitting the set of outputs. The conditions for using the proposed method are given. An example of synthesis is shown. The results of experiments with standard benchmarks are discussed. The experiments outcomes show that the proposed approach allows diminishing the number of LUTs and consumed energy. Also, it leads to an increase in the operating frequency. The method targets rather complex FSMs when the number of state variables exceeds the number of LUT's inputs.

Improving Characteristics of FSMs With Mixed Codes of Outputs

“…Very often, FSM circuits based on the structural decomposition have much better characteristics compared with their counterparts based on the functional decomposition [1], [17]. Our research [26], [27] shows that LUT-based FSM circuits with the mixed encoding of collections of outputs have better LUT counts than their counterparts based on the functional decomposition. But it is quite possible that there is more than a single level of LUTs in a circuit generating variables encoding of COs.…”

“…This phenomenon complicates the placement and routing process. This leads to rather slow FSM circuits with a high value of power consumption [24]- [26]. So, if condition ( 5) is violated, then the LUT count is equal to N +R S +N (F), where N (F) is the number of additional functions different from…”

“…But this is not only the way for reducing the power consumption. As shown in [24]- [26], the power consumption can be reduced by minimizing the number of interconnections inside an FSM circuit. To reduce the number of interconnections, it is necessary to minimize the numbers of arguments in SBFs ( 2)-( 3) [4].…”

“…Our current paper considers the synthesis of LUT-based Mealy FSMs obtained using the method of mixed encoding of outputs [9], [26]. The mixed encoding of outputs allows, reducing the LUT counts of FPGA-based Mealy FSMs compared with equivalent FSMs' circuits based on using the methods of functional decomposition [8].…”

Logic Synthesis Strategy Oriented to Low Power Optimization

“…Appropriately carried out selected synthesis steps can lead to a reduction in power consumption by programmable systems. This is especially visible in the case of the implementation of FSMs [23][24][25]. There are several ways to reduce power consumption when implementing FSM.…”