Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

Chu, Zhufei; Tang, Xianglu; Soeken, Mathias; Petkovska, Ana; Zgheib, Grace; Amarù, Luca; Xia, Yinshui; Ienne, Paolo; Micheli, Giovanni De; Gaillardon, Pierre-Emmanuel

doi:10.1145/3060403.3060432

Cited by 5 publications

(6 citation statements)

References 12 publications

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“…Researchers have also used carry chains without segment SUM outputs to map general logic equations into FPGAs, by using AND-Inverter-Graphs (AIG) [17] or Majority-Inverter-Graphs (MIG) [18] systems. Because of their reliance on example carry chain structures and focus on general equations, these systems tend to create slower and inefficient designs compared to our methodology, which systematically implements a set of specific N-sorter/N-filter equations on the target Fig.…”

Section: B Background: Carry Chain Logicmentioning

confidence: 99%

Use of Carry Chain Logic and Design System Extensions to Construct Significantly Faster and Larger Single-Stage N-sorters and N-filters

Kent¹

2022

Preprint

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We have recently introduced a general system for building fast single-stage hardware N-sorters and N-filters, with N?3. When N-sorter/N-filters designed with this system are constructed using a design logic block in the FPGA central to the Amazon AWS EC2 F1 instance, they were shown to be significantly faster than the prior state-of-the-art sorting devices, which are networks of 2-sorters and 2-filters. Here we show that N-sorter/N-filters are even faster when they are implemented using carry chain design logic blocks, featuring lookahead acceleration and dedicated routing, also found in the same FPGA product. A new 32-bit carry chain 7-sorter operates in 1.469 nS, a speedup of 1.23 versus our original state-of-the-art 7-sorter. Faster and larger N-sorters and much larger N-max/N-min filters are constructed when product term splitting and a new Sum-of-Products output multiplexer equation are added to the general design system, and then combined with carry chain logic. While we were previously limited to sorting 10 or fewer input values, we now fully sort 16 32-bit values in 2.024 nS, a speedup of 4.61 versus a comparable 2-sorter network. Our largest prior max pooling 32-bit N-max filter was a 9-max 3x3 2D image filter, but we have now produced a 125-max 5x5x5 3D video filter that operates in 2.075 nS, a speedup of 3.43 versus a 2-max network. Using 32-max single-stage filters, a 32-bit 1024-max 2-stage network operates in 3.557 nS, less than a 280 MHz clock’s period, and with a 2.85 speedup versus the equivalent 10-stage 2-max network.

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Section: B Background: Carry Chain Logicmentioning

confidence: 99%

Use of Carry Chain Logic and Design System Extensions to Construct Significantly Faster and Larger Single-Stage N-sorters and N-filters

Kent¹

2022

Preprint

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“…Although not all logic chains can be mapped onto carry chains, the results show that 9% of routing wires can be saved. Chu et al [21] propose a synthesis method that exploits carry chains for mapping general logic. The proposed technology mapping is based on majority-inverter graphs (MIGs).…”

Section: Related Workmentioning

confidence: 99%

“…This results on an average increment of the area-delay product of 9%. The main difference between this work and that presented in [21] is that, in the former, the technique is applied before the synthesis process while in the latter it is a post technology mapping approach.…”

Section: Related Workmentioning

confidence: 99%

Mapping Arbitrary Logic Functions onto Carry Chains in FPGAs

Senhadji-Navarro

García-Vargas

2021

Electronics

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Current Field Programmable Gate Arrays (FPGAs) provide fast routing links and special logic to perform carry operations; however, these resources can also be used to implement non-arithmetic circuits. In this paper, a new approach for mapping logic functions onto carry chains is presented. Unlike other approaches, the proposed technique can be applied to any logic function. The presented technique includes: (1) an architecture that is composed of blocks that implement AND and OR functions (called CANDs and CORs, respectively) by means of Look-Up-Tables (LUTs) and carry-chain resources; and (2) a mapping algorithm to reduce both the delay of the critical path and the number of used FPGA resources. The algorithm uses a heuristic to interconnect CORs and CANDs in order to reduce the delay. The problem of mapping the maxterms (or minterms) of a function to LUTs has been modelled as a Set Bin Packing (SBP) problem. Since SBP is NP-Hard, a greedy algorithm has been proposed, which is based on the First Fit Decreasing (FFD) heuristic. The results obtained have been compared with the conventional technique using both speed and area optimization. For this purpose, a large synthetic set of test cases has been generated. The proposed technique improves both the speed and area results for the vast majority of functions whose conventional implementation requires more than four logic levels. It is important to highlight that the improvement of one parameter (speed or area) is not achieved at the expense of the other.

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“…A single Ti-TcFET transistor can implement three input "majority-not" switch functions [26,27], and thus only one N-type Ti-TcFET and one P-type Ti-TcFET are needed to realize a "majority-not" logic cell, as shown in Figure 13a. From Figure 13a, the "majority-not" logic cell using traditional CMOS/FinFET devices needs 10 transistors.…”

Section: Logic Cells Based On Ti-tcfet Devicesmentioning

confidence: 99%

T-Channel Field Effect Transistor with Three Input Terminals (Ti-TcFET)

Chen

et al. 2020

Micromachines

Self Cite

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In this paper, a novel T-channel field effect transistor with three input terminals (Ti-TcFET) is proposed. The channel of a Ti-TcFET consists of horizontal and vertical sections. The top gate is above the horizontal channel, while the front gate and back gate are on either side of the vertical channel. The T-shaped channel structure increases the coupling area between the top gate and the front and back gates, which improves the ability of the gate electrodes to control the channel. What’s more, it makes the top gate have almost the same control ability for the channel as the front gate and the back gate. This unique structure design brings a unique function in that the device is turned on only when two or three inputs are activated. Silvaco technology computer-aided design (TCAD) simulations are used to verify the current characteristics of the proposed Ti-TcFET. The current characteristics of the device are theoretically analyzed, and the results show that the theoretical analysis agrees with the TCAD simulation results. The proposed Ti-TcFET devices with three input terminals can be used to simplify the complex circuits in a compact style with reduced counts of transistors compared with the traditional complementary metal–oxide–semiconductor/ fin field-effect transistors (CMOS/FinFETs) with a single input terminal and thus provides a new idea for future circuit designs.

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Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

Cited by 5 publications

References 12 publications

Use of Carry Chain Logic and Design System Extensions to Construct Significantly Faster and Larger Single-Stage N-sorters and N-filters

Use of Carry Chain Logic and Design System Extensions to Construct Significantly Faster and Larger Single-Stage N-sorters and N-filters

Mapping Arbitrary Logic Functions onto Carry Chains in FPGAs

T-Channel Field Effect Transistor with Three Input Terminals (Ti-TcFET)

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