Improving Diagnosis Efficiency via Machine Learning

Huang, Qicheng; Fang, Chenlei; Mittal, Soumya; Blanton, R. D.

doi:10.1109/test.2018.8624884

Cited by 19 publications

(5 citation statements)

References 21 publications

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“…To achieve this, the model prioritizes the fault case's prediction performance over that of the normal class. The classification of a process' normal class as the fault class is not fatal to the model, but it may have fatal repercussions if the fault class is classified as the normal class [23]. As a result, we assessed the model using the fault-class recall value.…”

Section: Fault Classificationmentioning

confidence: 99%

Alleviating Class-Imbalance Data of Semiconductor Equipment Anomaly Detection Study

et al. 2023

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Plasma-based semiconductor processing is highly sensitive, thus even minor changes in the procedure can have serious consequences. The monitoring and classification of these equipment anomalies can be performed using fault detection and classification (FDC). However, class imbalance in semiconductor process data poses a significant obstacle to the introduction of FDC into semiconductor equipment. Overfitting can occur in machine learning due to the diversity and imbalance of datasets for normal and abnormal. In this study, we suggest a suitable preprocessing method to address the issue of class imbalance in semiconductor process data. We compare existing oversampling models to reduce class imbalance, and then we suggest an appropriate sampling strategy. In order to improve the FC performance of plasma-based semiconductor process data, it was confirmed that the SMOTE-based model using an undersampling technique such as Tomek link is effective. SMOTE-TOMEK, which removes multiple classes and makes the boundary clear, is suitable for FDC to classify minute changes in plasma-based semiconductor equipment data.

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Section: Fault Classificationmentioning

confidence: 99%

Alleviating Class-Imbalance Data of Semiconductor Equipment Anomaly Detection Study

et al. 2023

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“…During the selection process, the importance of each feature is calculated as a measure of how much it reduces the weighted impurity in a tree. The calculated reductions are ranked over all features in the tree and averaged over all trees in a random forest [99]. Finally, the highest ranked features are selected for training a classification model.…”

Section: ) Software Defect Prediction Model Developmentmentioning

confidence: 99%

Improving Software Defect Prediction by Aggregated Change Metrics

et al. 2021

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To ensure the delivery of high quality software, it is necessary to ensure that all of its artifacts function properly, which is usually done by performing appropriate tests with limited resources. It is therefore desirable to identify defective artifacts so that they can be corrected before the testing process. So far, researchers have proposed various predictive models for this purpose. Such models are typically trained on data representing previous project versions of a software and then used to predict which of the software artifacts in the new version are likely to be defective. However, the data representing a software project usually consists of measurable properties of the project or its modules, and leaves out information about the timeline of the software development process. To fill this gap, we propose a new set of metrics, namely aggregated change metrics, which are created by aggregating the data of all changes made to the software between two versions, taking into account the chronological order of the changes. In experiments conducted on open source projects written in Java, we show that the stability and performance of commonly used classification models are improved by extending a feature set to include both measurable properties of the analyzed software and the aggregated change metrics.INDEX TERMS Classification, feature engineering, process metrics, change metrics, software defect prediction.

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“…The work in Huang, Fang, Mittal, and Blanton (2018) introduces a classifier to predict the following: (a) whether the failure log is at all useful for diagnosis, (b) the location of defects: scan‐chain or functional logic, and (c) the time needed for diagnosis. They have presented a set of features based on the failure log and used RF to design the classifier.…”

Section: Yield Learning and Diagnosismentioning

confidence: 99%

“…Three‐output classifiers where X is a feature vector with d elements, and y 1 , y 2 , and y 3 are discrete variables denoting the classes (Huang et al, 2018)…”

Section: Yield Learning and Diagnosismentioning

confidence: 99%

A survey of digital circuit testing in the light of machine learning

Pradhan

Bhattacharya

2020

WIREs Data Min & Knowl

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The insistent trend in today's nanoscale technology, to keep abreast of the Moore's law, has been continually opening up newer challenges to circuit designers. With rapid downscaling of integration, the intricacies involved in the manufacturing process have escalated significantly. Concomitantly, the nature of defects in silicon chips has become more complex and unpredictable, adding further difficulty in circuit testing and diagnosis. The volume of test data has surged and the parameters that govern testing of integrated circuits have increased not only in dimension but also in the complexity of their correlation. Evidently, the current scenario serves as a pertinent platform to explore new test solutions based on machine learning. In this survey, we look at various recent advances in this evolving domain in the context of digital logic testing and diagnosis. This article is categorized under: Algorithmic Development > Structure Discovery Technologies > Machine Learning Technologies > Prediction

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Improving Diagnosis Efficiency via Machine Learning

Cited by 19 publications

References 21 publications

Alleviating Class-Imbalance Data of Semiconductor Equipment Anomaly Detection Study

Alleviating Class-Imbalance Data of Semiconductor Equipment Anomaly Detection Study

Improving Software Defect Prediction by Aggregated Change Metrics

A survey of digital circuit testing in the light of machine learning

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