Improving dpa security by using globally-asynchronous locally-synchronous systems

Gürkaynak, Frank K.; Oetiker, S.; Kaeslin, Hubert; Felber, N.; Fichtner, W.

doi:10.1109/esscir.2005.1541646

Cited by 22 publications

(9 citation statements)

References 4 publications

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“…GALS based on pausible clocking is very interesting as a system integration technique. Some mature solutions have been developed [6] and practically evaluated [8]. Recently, this solution was also practically applied as a physical layer of one complex NoC system [9].…”

Section: Introductionmentioning

confidence: 99%

GALS for Bursty Data Transfer based on Clock Coupling

Krstić

Fan

Grass

et al. 2009

Electronic Notes in Theoretical Computer Science

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In this paper we introduce a novel burst-mode GALS technique. The goal of this technique is improving the performance of the GALS approach for systems with predominantly bursty data transfer. This new technique has been used to implement a GALS-based version of a hardware accelerator of a 60 GHz OFDM baseband processor. The simulation results show a significant performance improvement in comparison with a classical implementation of GALS using pausible clocking.

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Section: Introductionmentioning

confidence: 99%

GALS for Bursty Data Transfer based on Clock Coupling

Krstić

Fan

Grass

et al. 2009

Electronic Notes in Theoretical Computer Science

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“…The predominant soft cores that have been adopted as a co-processor for security applications or their internal architecture has been modified to accommodate new instructions for cryptographic algorithms are the LEON2 [22], LEON3 [11,12], Xtensa LX2 [21], Xtensa T1040 [19], and CoreMP7 [7].…”

Section: Comparisonsmentioning

confidence: 99%

“…The asynchrony in [16] has been used just for power reduction and not to mitigate side channel attacks. An example for the use of Globally Asynchronous Locally Synchronous in a cryptographic circuit as side channel attack countermeasure is given by [12]. However, the circuit in [12] is not for a programmable processor but for the implementation of the Advanced Encryption Standard (AES) [6] algorithm only.…”

Section: Introductionmentioning

confidence: 99%

GALS-based LPSP: Performance Analysis of a Novel Architecture for Low Power High Performance Security Processors

Farouk

El-Hadidi

Elfarag

2012

IJNC

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The past two decades have witnessed a revolution in the use of electronic devices in our daily activities. Increasingly, such activities involve the exchange of personal and sensitive data by means of portable and light weight devices. This implied the use of security applications in devices with tight processing capability and low power budget. Current architectures for processors that run security applications are optimized for either high-performance or low energy consumption. We propose an implementation for an architecture that not only provides high performance and low energy consumption but also mitigates security attacks on the cryptographic algorithms which are running on it. The proposed architecture of the GloballyAsynchronous Locally-Synchronous-based Low Power Security Processor (GALS-based LPSP) inherits the scheduling freedom and high performance from the dataflow architectures and the low energy consumption and flexibility from the GALS systems. In this paper, a prototype of the GALS-based LPSP is implemented as a soft core on the Virtex-5 (xc5-vlx155t) FPGA. The architectural features that allow the processor to mitigate Side-Channel attacks are explained in detail and tested on the current encryption standard, the AES. The performance analysis reveals that the GALS-based LPSP achieves two times higher throughput with one and a half times less energy consumption than the currently used embedded processors.

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“…Another common protection method is power trace misalignment, such as using a randomized clock [2], [8], [27], inserting random delays [4] and using multiple clock domains [9]. Randomized clock countermeasures use a single system clock which switches at random discrete time instants.…”

mentioning

confidence: 99%

“…Since this countermeasure uses single system clock for all memory elements, the power consumption caused by the memory elements at the clock switches, which usually dominates the overall consumption, is aligned and could be exploited by the attacker. Gürkaynak et al [9] proposed globally-asynchronous locally-synchronous implementation of AES composed of three blocks each having a local clock and a synchronization interface between them. The design is not generic; it is AES-specific and the blocks are hardwired.…”

mentioning

confidence: 99%

An EDA-Friendly Protection Scheme against Side-Channel Attacks

Bayrak

Velickovic

Regazzoni

et al. 2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-This paper introduces a generic and automated methodology to protect hardware designs from side-channel attacks in a manner that is fully compatible with commercial standard cell design flows. The paper describes a tool that artificially adds jitter to the clocks of the sequential elements of a cryptographic unit, which increases the non-determinism of signal timing, thereby making the physical device more difficult to attack. Timing constraints are then specified to commercial EDA tools, which restore the circuit functionality and efficiency while preserving the introduced randomness. The protection scheme is applied to an AES-128 hardware implementation that is synthesized using both ASIC and FPGA design flows.

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Improving dpa security by using globally-asynchronous locally-synchronous systems

Cited by 22 publications

References 4 publications

GALS for Bursty Data Transfer based on Clock Coupling

GALS for Bursty Data Transfer based on Clock Coupling

GALS-based LPSP: Performance Analysis of a Novel Architecture for Low Power High Performance Security Processors

An EDA-Friendly Protection Scheme against Side-Channel Attacks

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