-Pausible clocking based globally-asynchronous locally-synchronous (GALS) system design has been proven a promising approach to SoCs and NoCs. In this paper, we analyze the throughput reduction and synchronization failures introduced by the widely used pausible clocking scheme, and propose an optimized scheme for higher throughput and more reliable GALS design. The local clock generator is improved to minimize the acknowledge latency, and a novel input port is applied to maximize the safe timing region for the clock tree insertion. Simulation results using the IHP 0.13-µm standard CMOS process demonstrate that up to one-third increase in data throughput and an almost doubled safe timing region for clock tree distribution can be achieved in comparison to the traditional pausible clocking scheme.

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This paper presents an implementation of an integrated Ultra-wideband (UWB), Binary-Phase Shift Keying (BPSK) Gaussian modulated pulse generator. VCO, multiplier and passive Gaussian filter are the key components. The VCO provides the carrier frequency of 4.1 GHz, the LC Gaussian filter is responsible for the pulse shaping in the baseband. Multiplying the baseband pulse and the VCO frequency shifts the pulse to the desired center frequency. The generated Gaussian pulse ocupppies the frequency range from 3.1 to 5.1 GHz with the center frequency at 4.1 GHz. Simulations and measured results show that this spectrum fulfills the mask for indoor communication systems given by the FCC (Federal Communications Commission, 2002). The total power consumption is 55 mW using a supply voltage of 2.5 V. Circuits are realized using the IHP 0.25 µm SiGe:C BiCMOS technology.