A Cortex-M3 Based MCU Featuring AVS with 34nW Static Power, 15.3pJ/inst. Active Energy, and 16% Power Variation Across Process and Temperature

Salvador, Rubén; Sanchez, Alberto; Fan, Xin; Gemmeke, Tobias

doi:10.1109/esscirc.2018.8494312

Cited by 18 publications

(6 citation statements)

References 8 publications

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“…In 2018, In Ref. [34], an online monitoring method for Cortex-M3 microprocessors was put forward, which combined critical path replication and in-situ monitoring to deal with the effects of on-chip and inter-chip deviations.…”

Section: Research Status Of Indirect Monitoring Avfs Technologymentioning

confidence: 99%

Near-Threshold Wide-Voltage Design Review

Zhao

Yang

Chen

et al. 2023

Tsinghua Sci. Technol.

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This paper presents a comprehensive review of near-threshold wide-voltage designs on memory, resilient logic designs, low voltage Radio Frequency (RF) circuits, and timing analysis. With the prosperous development of wearable applications, low power consumption has become one of the primary challenges for IC designs. To improve the power efficiency, the prefer scheme is to operate at an ultra low voltage of Near Threshold Voltage (NTV). For the performance variation and degradation, a self-adaptive margin assignment technique is proposed in the low voltage. The proposed technique tracks the circuit states in real time and dynamically allocates voltage margins, reducing the minimum supply voltage and achieving higher energy efficiency. The self-adaptive margin assignment technique can be used in Static Random Access Memory (SRAM), digital circuits, and analog/RF circuits. Based on the self-adaptive margin assignment technique, the minimum voltage in the 40 nm CMOS process is reduced to 0.6 V or even lower, and the energy efficiency is increased by 3-4 times.

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Section: Research Status Of Indirect Monitoring Avfs Technologymentioning

confidence: 99%

Near-Threshold Wide-Voltage Design Review

Zhao

Yang

Chen

et al. 2023

Tsinghua Sci. Technol.

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“…Depending on whether the shadow element takes a sample before or after the clock-edge, the flagged error is either a predicted or real error respectively. Additionally, both samples can be taken simultaneously when a delay is added before the shadow element [5] resulting in another form of error prediction. To reduce the area impact of the detection, several works [13]- [16] integrate the shadow element into the sequential element as a transition detector (TD) that is activated during the DW.…”

Section: A Error Detectionmentioning

confidence: 99%

“…In (1), the system predicts timing errors rather than detecting them by monitoring for data transitions before the clock-edge. If this prediction is conservative enough, it simply acts as a warning signal that indicates that the system is close to its critical limit [5]. This completely removes the need for a correction method but introduces new margins.…”

Section: Error Correctionmentioning

confidence: 99%

Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

Uytterhoeven

Dehaene

2022

IEEE J. Solid-State Circuits

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This paper presents a timing error detection and correction (EDaC) technique optimized for near/sub-threshold operation to recover energy lost in the conventional signoff margins. The presented EDaC requires no modifications to the processor pipeline and avoids imposing additional holdconstraints on monitored paths by instantaneously checking for late activity. Further, two correction methods are discussed, a simple clock gating method and a low cycle overhead clock stretching method. Both provide robust last-minute error prevention. The EDaC is applied in a near/sub-threshold implementation of the CoolFlux DSP processor and infers only a 2.8 % and 2.1 % area overhead for the detection and correction respectively. Silicon measurements validate the EDaC system from 0.25 V to 0.7 V (1 MHz to 200 MHz) and show that it recovers all voltage margins in the near/sub-threshold region. The design achieves a MEP of 8.1 pJ/cycle at 0.34 V and 10 MHz. Here, the EDaC technique reduces the energy consumption by 48 % to 17.6 % with respect to the signoff margins depending on their conservatism, and it enables the processor to operate with only 12 % energy overhead compared to its ideal non-margined critical operation point.

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“…To control the temperature of chips, embedded systems usually use dynamic thermal management (DTM) techniques. These techniques usually try to adjust the processor voltage and frequency to control power consumption and temperature [3]- [5]. Many thermal management techniques have been proposed for modern chips due to increased power densities and reliability implications.…”

Section: Introductionmentioning

confidence: 99%

Temperature and performance evaluation of multiprocessors chips by optimal control method

2023

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Multi-core processors support all modern electronic devices nowadays. However, temperature and performance management are one of the most critical issues in the design of today’s microprocessors. In this paper, we propose a framework by using an optimal control method based on fan speed and frequency control of the multi-core processor. The goal is to optimize performance and at the same time avoid violating an expected temperature. Our proposed method uses a high-precision thermal and power model for multi-core processors. This method is validated on asymmetric ODROID-XU4 multi-core processor. The experimental results show the ability of the proposed method to achieve the adequate trade-off between performance and temperature control.

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A Cortex-M3 Based MCU Featuring AVS with 34nW Static Power, 15.3pJ/inst. Active Energy, and 16% Power Variation Across Process and Temperature

Cited by 18 publications

References 8 publications

Near-Threshold Wide-Voltage Design Review

Near-Threshold Wide-Voltage Design Review

Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

Temperature and performance evaluation of multiprocessors chips by optimal control method

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