Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT

Fan, Xin; Stuijt, Jan; Liu, Bo; Gemmeke, Tobias

doi:10.1109/tcsi.2018.2873026

Cited by 20 publications

(5 citation statements)

References 44 publications

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“…Of course, the performance can be improved by using larger size cells trading off with power consumption. It should also be noted that the LUT is possible to be configured externally for an actual chip by implementing a memory block like the all-standard-cellbased one in [31]. Then, similar automatic routine can be carried out on-chip or on-board to update the LUT values.…”

Section: B Transistor-configurable Inverter-based Rdac With Automated...mentioning

confidence: 99%

“…A reconfigurable memory-based LUT also helps alleviate other process-voltage-temperature (PVT) variations at the cost of memory size and complexity. For example, an implemented 1024 × 1024 memory-based LUT following [31] occupies about 0.255 mm 2 additional area. Alternatively, if a memory library were provided, the synthesized SRAM would be much smaller.…”

Section: B Transistor-configurable Inverter-based Rdac With Automated...mentioning

confidence: 99%

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An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

Ojima

et al. 2021

IEEE Trans. VLSI Syst.

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We propose an all-standard-cell-based synthesizable successive-approximation-register analog-to-digital converter (SAR ADC) which is automatically placed and routed (P&R) using a commercial digital implementation tool. For higher feasibility and wider input range, a differential architecture is proposed with an inverter-based resistive digital-to-analog converter (RDAC) and a four-input comparator. MOSFET gate capacitance is employed for the sampling capacitor. To mitigate its capacitance variation due to input voltage and the leakage between gate and diffusion, we leave the diffusion of the standard cell floating and only use the capacitance between gate and bulk. Two prototypes have been designed in 65-nm bulk CMOS. Prototype I has been fabricated and achieves 10 MS/s, 14.3 mW, and 28.1-dB SNDR in a 6-bit architecture. The performance is improved in Prototype II by proposing a lookup table (LUT)-compensating transistor-configurable inverter-based RDAC and an OR-AND-Inverter (OAI)-based comparator and by employing a thick-oxide diffusion-floating decoupling cell for the sampling capacitor. The default LUT is created during the design phase by a script-controlled automatic simulation routine. The power consumption is significantly reduced as well through improved timing control. Layout-parasitic-extraction (LPE) simulations of Prototype II suggest 35.7-and 47.2-dB SNDRs in 6-and 8-bit versions, respectively. The power consumptions are reduced to 0.91 and 2.52 mW, respectively.

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Section: B Transistor-configurable Inverter-based Rdac With Automated...mentioning

confidence: 99%

Section: B Transistor-configurable Inverter-based Rdac With Automated...mentioning

confidence: 99%

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

Ojima

et al. 2021

IEEE Trans. VLSI Syst.

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“…Synopsys Design Constraints (SDC) in the phase of logic synthesis will bring many uncertainties to the final performance, power, and area (PPA) results [5,6,7].…”

Section: Introductionmentioning

confidence: 99%

SIHM: Shuffled Iterative Hierarchical Minimixing for Parameter Space Generation Yielding Superior Pareto Points in Logic Synthesis

Liu,

Ling,

Zhu

2024

Preprint

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“…Another approach to multiported memory design is standard cell-based memory which utilizes Data Flip-Flop (DFF) or D-latch cells as memory elements [17]. While this technique has low design costs, it comes at the cost of very large area and power overhead [13,18,19]. Another actively researched approach in many core computing applications is utilizing the system interconnect for storing the data in local single ported caches to improve the memory accessibility.…”

Section: Introductionmentioning

confidence: 99%

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Golman,

Giterman,

Teman

2024

JLPEA

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Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for multi-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel multi-ported gain-cell design, which provides up-to N read ports and M independent write ports (NRMW). In addition, the proposed design features a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability, as well as a novel opportunistic refresh port approach. An 8kbit memory macro was implemented using a four-transistor bitcell with four ports (2R2W) in a 28 nm FD-SOI technology, offering up-to a 3× reduction in bitcell area compared to other dual-ported SRAM memory options, while also providing 100% memory availability, as opposed to conventional dynamic memories, which are hindered by limited availability.

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Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT

Cited by 20 publications

References 44 publications

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

SIHM: Shuffled Iterative Hierarchical Minimixing for Parameter Space Generation Yielding Superior Pareto Points in Logic Synthesis

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

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