Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection

Abstract

A gain-cell embedded DRAM (GC-eDRAM) is an attractive logic-compatible alternative to the conventional static random access memory (SRAM) for the implementation of embedded memories, as it offers higher density, lower leakage, and two-ported operation. However, it requires periodic refresh cycles to maintain its data which deteriorates due to leakage. The refresh-rate, which is traditionally set according to the worst cell in the array under extreme operating conditions, leads to a significant refresh power consumption and decreased memory availability. In this paper, we propose to reduce the cost of GC-eDRAM refresh by employing failure detection to lower the refresh-rate. A 4T dynamic complementary dual-modular redundancy bitcell is proposed to offer per-bit error detection, resulting in a substantial decrease in the refresh-rate and over 60% power reduction compared with the SRAM. The proposed approach is also compared with the conventional SRAM and GCeDRAM implementations with integrated error correction codes, demonstrating significant area and latency reductions. INDEX TERMS Error detection and correction, error correcting codes, SRAM, gain cells, logic-compatible eDRAM, GC-eDRAM, low power.

Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

“…As discussed in the previous Section 2, bit cells in conventional eDRAMs may cause data flipping instantly after the write operation due to a sub-threshold leakage current, which can be more severe in deep submicron technology [24][25][26][27][28]. Various methods have been suggested to address those issues; however, those approaches resulted in significant area overhead or needed additional voltage boosting circuits.…”