Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores

Swaminathan,; Kultursay,; Saripalli,; Narayanan,; Kandemir,; Datta,

doi:10.1109/islped.2011.5993644

Cited by 19 publications

(10 citation statements)

References 9 publications

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“…The scheme achieves average dynamic energy and leakage energy savings of 17% and 30%, respectively. However, the scheme has an overhead of performance degradation of 1% [21].…”

Section: Evolution Of Dvfsmentioning

confidence: 99%

A comparative study of voltage/frequency scaling in NoC

Usman

Khan

2013

IEEE International Conference on Electro-Information Technology , EIT 2013

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Abstract-Voltage and frequency is dynamically scaled to produce energy efficient multi-core networkon-chip (NoC). A detailed analysis of the techniques employed for this purpose are studied and based on the optimized performance the most effective ones are reported. We also highlight the most promising high performance and energy minimizing techniques.Index Terms-Network-on-chip, dynamic voltage and frequency scaling, leakage power

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“…The scheme achieves average dynamic energy and leakage energy savings of 17% and 30%, respectively. However, the scheme has an overhead of performance degradation of 1% [21].…”

Section: Evolution Of Dvfsmentioning

confidence: 99%

A comparative study of voltage/frequency scaling in NoC

Usman

Khan

2013

IEEE International Conference on Electro-Information Technology , EIT 2013

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“…OFF-state leakage current and ON current of TFET and CMOS when VCC is (a) 0.3V and (b) 0.7V (adapted from [13])…”

Section: 2tunneling Field Effect Transistors (Tfets)mentioning

confidence: 99%

“…There have been several studies on building hybrid storage-cell based structure and furthermore, heterogeneous multi-core processors based on CMOS and TFETs to achieve the good trade-off between performance and power [13,19,27,28]. For instance, Narayanan et al [19] developed the hybrid cache architecture that uses a mix of TFET and the non-volatile memory.…”

Section: Related Workmentioning

confidence: 99%

“…For instance, Narayanan et al [19] developed the hybrid cache architecture that uses a mix of TFET and the non-volatile memory. Swaminathan et al [13] proposed to replace some of the CMOS cores with TFET alternatives, and dynamically migrate threads between CMOS and TFET cores to achieve significant energy savings with negligible performance loss. We build the hybrid registers in GPGPU Baseline CMOS_RA MEM_RA and leverage its unique characteristics to fully explore the benefit of TFETs for the energy-efficient GPGPU design.…”

Section: Related Workmentioning

confidence: 99%

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Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Tan

2013

International Symposium on Quality Electronic Design (ISQED)

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State-of-the-art General-Purpose computing on Graphics Processing Unit (GPGPU) is facing severe power challenge due to the increasing number of cores placed on a chip with decreasing feature size. In order to hide the long latency operations, GPGPU employs the fine-grained multithreading among numerous active threads, leading to the sizeable register files with massive power consumption. Exploring the optimal power savings in register files becomes the critical and first step towards the energyefficient GPGPUs. The conventional method to reduce dynamic power consumption is the supply voltage scaling, and the inter-bank tunneling FETs (TFETs) are the promising candidates compared to CMOS for low voltage operations regarding to both leakage and performance. However, always executing at the low voltage (so that low frequency) will result in significant performance degradation. In this study, we propose the hybrid CMOS-TFET based register files. To optimize the register power consumption, we allocate TFET-based registers to threads whose execution progress can be delayed to some degree to avoid the memory contentions with other threads, and the CMOS-based registers are still used for threads requiring normal execution speed. Our experimental results show that the proposed technique achieves 30% energy (including both dynamic and leakage) reduction in register files with little performance degradation compared to the baseline case equipped with naive power optimization technique.

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“…For cores, we assumed a simple in-order core model and calculated its energy using the method in [20]. In order to model our caches, we used various simulators.…”

Section: Core and Cache Modelingmentioning

confidence: 99%

Design space exploration of workload-specific last-level caches

Swaminathan

Kültürsay

Saripalli

et al. 2012

Proceedings of the 2012 ACM/IEEE International Symposium on Low Power Electronics and Design

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Leakage power of last-level caches constitute a significant part of overall power consumption. Various circuit-level and technology-based methods have been proposed to reduce cache leakage. However, from a system designer's perspective, for a particular configuration and workload, it is not clear which method will be most effective. In this work, we make a detailed evaluation and comparison of cache energy reduction techniques. Our results show that when energy is very scarce and important, the best results are obtained with highly energy efficient Tunnel-FET caches. When the available energy increases and performance becomes a bigger concern, there is no single winner. While a small number of capacity sensitive workloads benefit from increased capacity of STT-RAM caches, latency sensitive workloads prefer solutions with smaller latency penalties such as drowsy caches.

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Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores

Cited by 19 publications

References 9 publications

A comparative study of voltage/frequency scaling in NoC

A comparative study of voltage/frequency scaling in NoC

Hybrid CMOS-TFET based register files for energy-efficient GPGPUs

Design space exploration of workload-specific last-level caches

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