Improving FPGA Performance and Area Using an Adaptive Logic Module

Hutton, Mike; Schleicher, Jay; Lewis, David; Pedersen, Bruce; Yuan, Richard; Kaptanoglu, Sinan; Baeckler, Gregg; Ratchev, Boris; Padalia, Ketan; Bourgeault, Mark; Lee, Andy; Kim, Henry; Saini, Rahul

doi:10.1007/978-3-540-30117-2_16

Cited by 48 publications

(32 citation statements)

References 16 publications

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“…The global routing architecture is built with Connection Blocks (CBs), which connect CLB pins to routing tracks, and Switch Boxes (SBs), which interconnect routing tracks. Inside a CLB, there are a number of Basic Logic Elements (BLEs) each of which consists of a fracturable Look Up Table (LUT) [14], a D Flip-flop (FF), and a output selector (2:1 MUX). Additionally, there is a local routing architecture interconnects BLE pins and CLB pins.…”

Section: B Rram-based Fpga Architecturementioning

confidence: 99%

Accurate power analysis for near-V<inf>t</inf> RRAM-based FPGA

Tang

Gaillardon

Micheli

2015

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-Resistive Random Access Memory (RRAM)-based FPGA architectures employ RRAMs not only as memories to store the configuration but embed them in the datapaths of programmable routing resources to propagate signals with improved performances. Sources of power consumption have been intensively studied for conventional Static Random Access Memories (SRAM)-based FPGAs. However, very limited works focused so far on studying the power characteristics of RRAM-based FPGAs. In this paper, we first analyze the power characteristics of RRAM-based multiplexer at circuit level and then use electrical simulations to study power consumption of RRAM-based FPGA architectures. Experimental results show that RRAM-based FPGAs achieve a Power-Delay Product reduced by 50% compared to SRAM-based FPGA at nominal voltage and 20% compared to near-Vt SRAM-based FPGA, respectively.

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Section: B Rram-based Fpga Architecturementioning

confidence: 99%

Accurate power analysis for near-V<inf>t</inf> RRAM-based FPGA

Tang

Gaillardon

Micheli

2015

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

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“…As the CMOS device technology scales into deep-submicron domain, many vendors recognize that wider LUT may provide better trade-off between critical path delay and logic density. As a result, the Xilinx Virtex-5 [22] offers 6-input LUTs with fully independent inputs and the Altera Stratix II [13] provides an 8-input fracturable LUT. However, wide-gating functions in [22,13] come with a price.…”

Section: Variable-size Lutsmentioning

confidence: 99%

“…As a result, the Xilinx Virtex-5 [22] offers 6-input LUTs with fully independent inputs and the Altera Stratix II [13] provides an 8-input fracturable LUT. However, wide-gating functions in [22,13] come with a price. First, the widegating functions are enabled through use of extra dedicated circuitry, which itself adds the hardware cost and can be wasted if not used.…”

Section: Variable-size Lutsmentioning

confidence: 99%

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The amorphous FPGA architecture

Lin

2008

Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays

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This paper describes the Amorphous FPGA, an innovative architecture attempting to optimally allocate logic and routing resource on per-mapping basis. Designed for high performance, routability, and ease-of-use, it supports variablegranularity logic blocks, dedicated wide multiplexers, and variable-length bypassing interconnects with a symmetrical structure. Due to its many unconventional architectural features, the amorphous FPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new placement algorithm and a modified delay-based routing procedure. It is shown that, on average, an FPGA with the amorphous architecture can achieve a 1.35 times improvement in logic density, 9% improvement in average net delay, and 4% improvement in the critical-path delay for the largest 20 MCNC benchmark circuits over an island-style baseline.

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“…Commercial FPGAs [17]- [19] widely support fracturable LUTs [20] to reduce the critical path. In this paper, we typically consider FPGA consisting of K = 6 fracturable LUTs organized in logic blocks described by N = 10, I = 33.…”

Section: Introductionmentioning

confidence: 99%

A high-performance low-power near-Vt RRAM-based FPGA

Tang

Gaillardon

Micheli

2014

2014 International Conference on Field-Programmable Technology (FPT)

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Abstract-The routing architecture, heavily using programmable switches, dominates the area, delay and power of Field Programmable Gate Arrays (FPGAs). Resistive Random Access Memories (RRAMs) enable high-performance routing architectures through the replacement of Static Random Access Memory (SRAM)-based programming switches. Exploiting the very low on-resistance state achievable by RRAMs, RRAM-based routing multiplexers can be used to significantly reduce the FPGA routing delays. In addition, RRAM-based routing architectures are less sensitive to supply voltage reductions and show promises in low-power FPGA designs. In this paper, we propose a nearVt low-power RRAM-based FPGA where both delay and power reductions are achieved. Experimental results demonstrate that a near-Vt RRAM-based FPGA design leads to a 15% area shrink, a 10% delay reduction, and a 65% power improvement, compared to a conventional FPGA design for a given technology node. To achieve low on-resistance values, RRAMs typically require high programming currents. In other word, they need relatively large programming transistors, potentially resulting in area, delay and power inefficiencies. We also present a design methodology to properly size the programming transistors of RRAMs in order to further improve the area-efficiency. Experimental results show that a correct programming transistor sizing strategy contributes to further 18% area and 2% delay shrink, compared to the initial near-Vt RRAM-based FPGA.

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Improving FPGA Performance and Area Using an Adaptive Logic Module

Cited by 48 publications

References 16 publications

Accurate power analysis for near-V<inf>t</inf> RRAM-based FPGA

Accurate power analysis for near-V<inf>t</inf> RRAM-based FPGA

The amorphous FPGA architecture

A high-performance low-power near-Vt RRAM-based FPGA

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