Improving high level synthesis optimization opportunity through polyhedral transformations

Abstract

High level synthesis (HLS) is an important enabling technology for the adoption of hardware accelerator technologies. It promises the performance and energy efficiency of hardware designs with a lower barrier to entry in design expertise, and shorter design time. State-of-the-art high level synthesis now includes a wide variety of powerful optimizations that implement efficient hardware. These optimizations can implement some of the most important features generally performed in manual designs including parallel hardware units, pipelining of execution both within a hardware unit and between units, and fine-grained data communication. We may generally classify the optimizations as those that optimize hardware implementation within a code block (intra-block) and those that optimize communication and pipelining between code blocks (interblock). However, both optimizations are in practice difficult to apply. Real-world applications contain data-dependent blocks of code and communicate through complex data access patterns. Existing high level synthesis tools cannot apply these powerful optimizations unless the code is inherently compatible, severely limiting the optimization opportunity.In this paper we present an integrated framework to model and enable both intra-and inter-block optimizations. This integrated technique substantially improves the opportunity to use the powerful HLS optimizations that implement parallelism, pipelining, and fine-grained communication. Our polyhedral model-based technique systematically defines a set of data access patterns, identifies effective data access patterns, and performs the loop transformations to enable the intra-and inter-block optimizations. Our framework automatically explores transformation options, performs code transformations, and inserts the appropriate HLS directives to implement the HLS optimizations. Furthermore, our framework can automatically generate the optimized communication blocks for fine-grained communication between hardware blocks. Experimen- * Corresponding Author Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. FPGA '13, February 11-13, 2013, Monterey, California, USA. Copyright 2013 ACM 978-1-4503-1887 tal evaluation demonstrates that we can achieve an average of 6.04X speedup over the high level synthesis solution without our transformations to enable intra-and inter-block optimizations.

Polyhedral-based data reuse optimization for configurable computing

“…Recently, the importance of considering platform-dependent cost modeling in optimizing the loop transformation has been emphasized [32,41]. Loop transformation and data reuse optimization are loosely coupled by introducing fast hierarchical memory size estimators [26,33] to evaluate the promising transformations.…”

Exploiting vectorization in high level synthesis of nested irregular loops

“…Identification of this type of loops can be performed by means of Polyhedral methodologies, which allow to analyze and transform source code specifications exposing the different possibilities of parallelizing a loop. An example of framework aiming at performing such type of transformations is presented in [2]: this framework is able to systematically identify effective access patterns and to apply both inter-and intra-block optimizations, exposing several types of possible parallelization. The framework then evaluates each of them, and when estimated it as profitable, applies it to the specification source code.…”

“…An important class of loops which are good candidates to be parallelized are DoAll loops [2]. These loops are characterized by the absence of inter-iteration dependences which allows completely independent execution of different iterations.…”

Exploiting Outer Loops Vectorization in High Level Synthesis

“…Identification of this type of loops can be performed by means of Polyhedral methodologies, which allow to analyze and transform source code specifications exposing the different possibilities of parallelizing a loop. An example of framework aiming at performing such type of transformations is presented in [19]: this framework is able to systematically identify effective access patterns and to apply both inter-and intra-block optimizations, exposing several types of possible parallelization. The framework then evaluates each of them, and when estimated it as profitable, applies it to the specification source code.…”

“…An important class of loops which are good candidates to be parallelized are DoAll loops [19]. These loops are characterized by the absence of interiteration dependences which allows completely independent execution of different iterations.…”