Improving HLS Generated Accelerators Through Relaxed Memory Access Scheduling

Rohde, Johanna; Müller, Karsten; Hochberger, Christian

doi:10.1109/ipdpsw50202.2020.00020

Cited by 1 publication

(1 citation statement)

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“…Yet, most of these techniques have not been incorporated in current High-Level Synthesis (HLS) compilers [10], [11], [12], so, recently, many works have focused on applying them to HLS design and tools. Bypasses from write to read operations were proposed in [13] to improve scheduling when Read-after-Write (RAW) dependencies were present. As a result, II can be reduced down to the processing logic latency, eliminating the memory latencies from the equation.…”

Section: Introductionmentioning

confidence: 99%

Enhancing Conditional Stalling to Boost Performance of Stream-Processing Logic With RAW Dependencies

Alonso¹,

Sutter²,

López-Buedo³

et al. 2023

IEEE Trans. Circuits Syst. II

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Ambiguous read-after-Write (RAW) dependencies are omnipresent in multiple streaming applications, establishing hard to optimize bottlenecks. Considering actual input data, these may rarely be true dependencies. However, the increasingly used High-Level Synthesis (HLS) compilers must assume the worstcase scenario, as they rely on static optimizations. Conditional stalling is a simple yet impactful technique, useful even when conflicts are common. At the cost of a small area penalty, it allows improving (in some cases, by several times) the mean throughput of these systems. In this brief, we describe a high-frequency HLS implementation of the technique and examine its behavior as a function of input and architecture characteristics, with the goal of understanding when to use it and how to optimize throughput.

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Section: Introductionmentioning

confidence: 99%