Improving IEEE 1588v2 time synchronization performance with phase locked loop

Abstract

IEEE 1588 is one of the packet-based clock synchronization protocols. This protocol claims to achieve submicrosecond clock accuracy in the implementation. However there are several factors that causes the clock synchronization process not be performed accurately. Different clock quality in each device will cause inaccurate clock synchronization. In order to mitigate such kind of error, Phase Locked Loop (PLL) could be the solution of it. However, in some previous work, this method requires long time to achieve stable clock synchronization. In this paper, we propose a method that consists of combination of IEEE 1588 and PLL to mitigate both queuing delay variation from the network congestion as well as clock error because of the clock drift. OMNeT++ based simulation has been performed to verify our proposed method. The experiments show that our method achieved sub-microsecond clock accuracy in faster period than the existing method.

IEEE 1588 for Clock Synchronization in Industrial IoT and Related Applications: A Review on Contributing Technologies, Protocols and Enhancement Methodologies

“…On the contrary to switches or router, master and slave clocks are end nodes in the network [47]. The worst condition of the queuing delay happens in switches or routers [48][49][50]. Figure 6 represents a complete PTP network employing all kinds of PTP clocks, their port states (Master/Slave), and the positions in the network.…”