IEEE 1588 is one of the packet-based clock synchronization protocols. This protocol claims to achieve submicrosecond clock accuracy in the implementation. However there are several factors that causes the clock synchronization process not be performed accurately. Different clock quality in each device will cause inaccurate clock synchronization. In order to mitigate such kind of error, Phase Locked Loop (PLL) could be the solution of it. However, in some previous work, this method requires long time to achieve stable clock synchronization. In this paper, we propose a method that consists of combination of IEEE 1588 and PLL to mitigate both queuing delay variation from the network congestion as well as clock error because of the clock drift. OMNeT++ based simulation has been performed to verify our proposed method. The experiments show that our method achieved sub-microsecond clock accuracy in faster period than the existing method.

Clock or time synchronization protocol is one of the crucial factors that could determine the quality of the communication. With the rapid development of the network technology, more robust clock synchronization algorithm is required. IEEE 1588 is one of the possible solutions for a robust clock synchronization algorithm; however, there are still some challenges that need to be concerned in IEEE 1588 in term of reducing and stabilizing the PDV value. This survey paper shows several solutions that could improve the performance of IEEE 1588, including modifying the PTP message transmission, optimizing PTP method, filtering techniques, and using the hardware timestamp instead of application layer timestamp, and so on. Despite the improvement that is created with these techniques, the clock synchronization algorithm is still an open issue in the network communication.