Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation

Davidson, Jack W.; Jinturkar, Sanjay

doi:10.1109/micro.1995.476820

Cited by 23 publications

(13 citation statements)

References 10 publications

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“…Set II benchmarks consist of a number of kernels and applications from an embedded systems domain with high InstructionLevel Parallelism (ILP). Certain transformations such as loop unrolling [Davidson and Jinturkar 1995], constant folding, and tree height reduction [Mahlke et al 1992] are used to further enhance the ILP of Set II benchmark applications.…”

Section: Methodsmentioning

confidence: 99%

Shared-port register file architecture for low-energy VLIW processors

Goel

Kumar

Panda

2014

ACM Trans. Archit. Code Optim.

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We propose a reduced-port Register File (RF) architecture for reducing RF energy in a VLIW processor. With port reduction, RF ports need to be shared among Function Units (FUs), which may lead to access conflicts, and thus, reduced performance. Our solution includes (i) a carefully designed RF-FU interconnection network that permits port sharing with minimum conflicts and without any delay/energy overheads, and (ii) a novel scheduling and binding algorithm that reduces the performance penalty. With our solution, we observed as much as 83% RF energy savings with no more than a 10% loss in performance for a set of Mediabench and Mibench benchmarks.

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Section: Methodsmentioning

confidence: 99%

Shared-port register file architecture for low-energy VLIW processors

Goel

Kumar

Panda

2014

ACM Trans. Archit. Code Optim.

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“…To eliminate the modulo operator used in the buffers access function, the loop unrolling technique [Carr et al 1996;Davidson and Jinturkar 1995] is used, (i.e., the block assigned to each processor is divided into several sub blocks along the first axis and the loop scanning these subblocks along the first axis is completely unrolled). The unrolling factor is given by the size of the buffer.…”

Section: Elimination Of Modulo Operatorsmentioning

confidence: 99%

MPSoC memory optimization using program transformation

Bouchebaba

Girodias

Nicolescu

et al. 2007

ACM Trans. Des. Autom. Electron. Syst.

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Multiprocessor system-on-a-chip (MPSoC) architectures have received a lot of attention in the past years, but few advances in compilation techniques target these architectures. This is particularly true for the exploitation of data locality. Most of the compilation techniques for parallel architectures discussed in the literature are based on a single loop nest. This article presents new techniques that consist in applying loop fusion and tiling to several loop nests and to parallelize the resulting code across different processors. These two techniques reduce the number of memory accesses. However, they increase dependencies and thereby reduce the exploitable parallelism in the code. This article tries to address this contradiction. To optimize the memory space used by temporary arrays, smaller buffers are used as a replacement. Different strategies are studied to optimize the processing time spent accessing these buffers. The experiments show that these techniques yield a significant reduction in the number of data cache misses (30%) and in processing time (50%).

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“…This transformation reduces overhead of loop execution such as test testing for loop termination condition and can improve instruction scheduling and other optimization. Impact of loop unrolling on Instruction Buffer size was studied in [16] [7]. The obvious impact of use of the loop unrolling is the increase of the size of the resulting code.…”

Section: Introductionmentioning

confidence: 99%

Effects of loop unrolling and use of instruction buffer on processor energy consumption

Guzma

Pitkänen

Takala

2011

2011 International Symposium on System on Chip (SoC)

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In the area of Embedded Systems, instruction memories are one of the critical components consuming significant amounts of energy. Existence of a relation between size of the compiled program, and consequently required size of the instruction memory, and the compiler optimization flags is wellknown. In particular, loop transformations such as loop unrolling, while having potential to increase performance dramatically, often cause unreasonable growth in the size of the required instruction memory, causing loss of benefit of lower cycle count from overall system energy point of view.One method how to decrease energy consumption of the memories is use of instruction buffers. Often executed loops are stored in the buffer and executed from there, while main memory is not read.In this paper, we show how the compiler flag, controlling loop unrolling, influences the structure of the loops in the program. While unrolling improves performance, unrolled loops can disappear from the program completely, or grow to unreasonable size where use of instruction buffer brings no benefits from the energy point of view.978-1-4577-0672-1/11/$26.00 c 2011 IEEE

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Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation

Cited by 23 publications

References 10 publications

Shared-port register file architecture for low-energy VLIW processors

Shared-port register file architecture for low-energy VLIW processors

MPSoC memory optimization using program transformation

Effects of loop unrolling and use of instruction buffer on processor energy consumption

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