Improving logic density through synthesis-inspired architecture

Abstract

We leverage properties of the logic synthesis netlist to define both a logic element architecture and an associated technology mapping algorithm that together provide improved logic density. We demonstrate that an "extended" logic element with slightly modified K-input LUTs achieves much of the benefit of an architecture with K+1-input LUTs, while consuming silicon area close to a K-LUT (a K-LUT requires half the area of a K+1-LUT). We introduce the notion of "non-inverting paths" in a circuit's AND-inverter graph (AIG) and show their utility in mapping into the proposed logic element. Results show that while circuits mapped to a traditional 5-LUT architecture need 14% more LUTs and have 12% more depth than a 6-LUT architecture, our extended 5-LUT architecture requires only 7% more LUTs and 2.5% more depth than 6-LUTs, on average. Nearly all of the depth reduction associated with moving from K-input to K+1-input LUTs can be achieved with considerably less area using extended K-LUTs. We further show that 6-LUT optimal mapping depths can be achieved with a small fraction of the LUTs in hardware being 6-LUTs and the remainder being extended 5-LUTs, suggesting that a heterogeneous logic block architecture may prove to be advantageous.

Area-efficient FPGA logic elements: Architecture and synthesis

“…The 0-cofactor with respect to c is: y c = 1 and therefore: |y c | = 0. Note that the extended 5-LUT here has broader application versus that described in our prior work [12]; the prior work only considered gating inputs that force a function to logic-0.…”

“…The element is more restrictive than the 5+4-LUT element as it requires the presense of a gating input to implement a 6-variable function. We refer to the element as an extended 5-LUT -a term we introduced in our prior work [12]. To understand this element, consider the AIG example of Fig.…”

A case for hardened multiplexers in FPGAs

“…between 4 and 6 is typically seen in industry and academia, and this range has been demonstrated to offer a good area/performance compromise [1], [2]. Recently, a number of other works have explored alternative FPGA logic element architectures for performance improvement [3], [4], [5], [6], [7] to close the large gap between FPGAs and ASICs [8]. In this paper, we propose incorporating (some) hardened multiplexers in FPGA logic blocks as a means of increasing silicon area efficiency and logic density.…”

FPGA power reduction by guarded evaluation

“…In [5], we generalized the gating input idea and observed that the defining feature of such inputs is the presence of a non-inverting path from the input through the AIG to the root node of the AIG. Since by definition, an AIG contains only AND gates with inversions on some edges, one does not need to be concerned with other gates appearing in the AIG (e.g.…”

“…Gating inputs to LUTs can be easily discovered through a traversal of a LUT's underlying AIG. In [5], the notions of gating inputs and non-inverting paths were applied to map circuits into a new logic block architecture that delivers improved area-efficiency. Here, we apply the ideas for a different purpose, namely, power reduction through guarded evaluation.…”