Improving Performance and Fabrication Metrics of Three-Dimensional ICs by Multiplexing Through-Silicon Vias

A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias

“…Therefore TH should be selected such that; TH TCLK in general. The proof of this concept and more detailed analysis are in [1]. Fig.…”

“…1b, is used to control the circuit. Referring to [1], using the TSVBOX circuit, V1 and V2 signals can be transferred over one TSV instead of two as in the conventional 3D-ICs. Ideally, V2 will pass with no delay, thus V2 =V2, and V1 will be delayed by TH so V1 (t)=V1(t − TH ).…”

“…Therefore almost 50% reduction in TSV count is achieved. Due to this significant reduction in TSV count, the analysis done in [1] on yield has revealed very high improvement over conventional 3D-ICs. The TSVBOX uses extra selection signal (SEL) to control a multiplexer/demultiplexer assembly.…”

“…Such delay may affect the functional validity of the system to be implemented using TSVBOX. Although, [1] addresses most of the issues related to TSVs multiplexing, such delay problem has not been studied yet. Due to its scalability and novelty as a multicore communication architecture for future multiprocessor SoCs, 3D NoC is selected as our target system architecture for applying the TSVBOX technique.…”

“…Hence, finding a technique that reduces TSV count without affecting the benefits gained by 3D integration is crucial. The TSV multiplexing technique introduced in [1] reduces the number of TSVs by half, by multiplexing each two 3D signals 1 into one signal and passing this signal through one TSV instead of two. Therefore almost 50% reduction in TSV count is achieved.…”