Thermal analysis of three-dimensional ICs, investigating the effect of through-silicon vias and fabrication parameters

Said, Mostafa; Mehdipour, Farhad; El-Sayed, Mohamed

doi:10.1109/edaps.2013.6724415

Cited by 3 publications

(3 citation statements)

References 8 publications

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“…26 is very close to 1, showing no improvement in die yield but very small degradation. This degradation is increasing with the number of layers used, and it is only clear for large M 6 . The enhancement in TSV yield is dependent mainly on the number of TSVs.…”

Section: F Yield Enhancement and Cost Reduction Versus Data Bus Widtmentioning

confidence: 99%

“…Such delay may affect the functional validity of the system to be implemented using TSVBOX. Although, [1,6,7] address most of the issues related to TSVs multiplexing and show the advantages and limitations of this technique, the timing requirements and the design methodology based on TSV multiplexing have not been studied yet. None of the above related works shows any system implementation of a circuit using TSVBOX, so its functionality and applicability in system level have not been proven yet.…”

Section: Introductionmentioning

confidence: 99%

“…In [6,7], other physical effects of reducing TSV count are studied. In [6], the impact of reducing TSV count on maximum temperature is investigated, and as expected the maximum temperature increases as the TSV count decreases. TSVs are usually fabricated using low thermal resistivity materials such as copper or tungsten [2].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

Said

Shalaby

Mehdipour

et al. 2016

Microprocessors and Microsystems

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Abstract-The use of short Through-Silicon Vias (TSVs) in 3D integration Technology introduces a significant reduction in routing area, power consumption, and delay. Although, there are still several challenges in 3D integration technology; mainly low yield, which is a direct result of extra fabrication steps of TSVs. Therefore, reducing TSV count has a considerable effect on improving yield and hence reducing cost. A TSV multiplexing technique called TSVBOX was introduced in [1] to reduce the TSV count without affecting the direct benefits of TSVs. Although, the TSVBOX introduces some delay to the signals to be multiplexed, this delay effect of TSV multiplexing is not addressed yet. In this paper, we analyze the TSVBOX timing requirements and propose a design methodology for TSVBOXbased 3D Network-on-Chip (NoC). Then performance and power comparisons are conducted to investigate the direct effects of TSV multiplexing on these two metrics. After that the basic fabrication metrics are compared to investigate the effect of the proposed design methodology on yield and cost. We show that the TSVBOX extremely enhances the fabrication metrics at minimal degradation in performance and power consumption, especially for Hotspot-like traffic patterns.

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Section: F Yield Enhancement and Cost Reduction Versus Data Bus Widtmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

Said

Shalaby

Mehdipour

et al. 2016

Microprocessors and Microsystems

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Using TSVs for thermal mitigation in 3D circuits: Wish and truth

Santos

Souare

Crecy

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

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Modeling Thermal Microspreading Resistance in Via Arrays

Fish

McCluskey

Bar‐Cohen

2016

Journal of Electronic Packaging

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As thermal management techniques for three-dimensional (3D) chip stacks and other high-power density electronic packages continue to evolve, interest in the thermal pathways across substrates containing a multitude of conductive vias has increased. To reduce the computational costs and time in the thermal analysis of through-layer via (TXV) structures, much research to date has focused on defining effective anisotropic thermal properties for a pseudohomogeneous medium using isothermal boundary conditions. While such an approach eliminates the need to model heat flow through individual vias, the resulting properties are found to depend on the specific boundary conditions applied to a unit TXV cell. More specifically, effective properties based on isothermal boundary conditions fail to capture the local “microspreading” resistance associated with more realistic heat flux distributions and local hot spots on the surface of these substrates. This work assesses how the thermal microspreading resistance present in arrays of vias in interposers, substrates, and other package components can be properly incorporated into the modeling of these arrays. We present the conditions under which spreading resistance plays a major role in determining the thermal characteristics of a via array and propose methods by which designers can both account for the effects of microspreading resistance and mitigate its contribution to the overall thermal behavior of such substrate–via systems. Finite element modeling (FEM) of TXV unit cells is performed using commercial simulation software (ansys).

show abstract

Thermal analysis of three-dimensional ICs, investigating the effect of through-silicon vias and fabrication parameters

Cited by 3 publications

References 8 publications

A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

A design methodology and various performance and fabrication metrics evaluation of 3D Network-on-Chip with multiplexed Through-Silicon Vias

Using TSVs for thermal mitigation in 3D circuits: Wish and truth

Modeling Thermal Microspreading Resistance in Via Arrays

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