While component dissipation patterns and system operating modes vary widely, many electronic packaging configurations can be modeled by symmetrically or asymmetrically isothermal or isoflux plates. The idealized configurations are amenable to analytic optimization based on maximizing total heat transfer per unit volume or unit primary area. To achieve this anlaytic optimization, however, it is necessary to develop composite relations for the variation of the heat transfer coefficient along the plate surfaces. The mathematical development and verification of such composite relations as well as the formulation and solution of the optimizing equations for the various boundary conditions of interest constitute the core of this presentation.

In present-day high-performance electronic components, the generated heat loads result in unacceptably high junction temperatures and reduced component lifetimes. Thermoelectric modules can, in principle, enhance heat removal and reduce the temperatures of such electronic devices. However, state-of-the-art bulk thermoelectric modules have a maximum cooling flux qmax of only about 10 W cm−2, while state-of-the art commercial thin-film modules have a qmax <100 W cm−2. Such flux values are insufficient for thermal management of modern high-power devices. Here we show that cooling fluxes of 258 W cm−2 can be achieved in thin-film Bi2Te3-based superlattice thermoelectric modules. These devices utilize a p-type Sb2Te3/Bi2Te3 superlattice and n-type δ-doped Bi2Te3−xSex, both of which are grown heteroepitaxially using metalorganic chemical vapour deposition. We anticipate that the demonstration of these high-cooling-flux modules will have far-reaching impacts in diverse applications, such as advanced computer processors, radio-frequency power devices, quantum cascade lasers and DNA micro-arrays.

Thermal interface materials (TIMs) play a critical role in conventionally packaged electronic systems and often represent the highest thermal resistance and/or least reliable element in the heat flow path from the chip to the external ambient. In defense applications, the need to accommodate large differences in the coefficients of thermal expansion (CTE) among the packaging materials, provide for in-field reworkability, and assure physical integrity as well as long-term reliability further exacerbates this situation. Epoxy-based thermoplastic TIMs are compliant and reworkable at low temperature, but their low thermal conductivities pose a significant barrier to the thermal packaging of high-power devices. Alternatively, while solder TIMs offer low thermal interface resistances, their mechanical stiffness and high melting points make them inappropriate for many of these applications. Consequently, Defense Advanced Research Projects Agency (DARPA) initiated a series of studies exploring the potential of nanomaterials and nanostructures to create TIMs with solderlike thermal resistance and thermoplasticlike compliance and reworkability. This paper describes the nano-TIM approaches taken and results obtained by four teams responding to the DARPA challenge of pursuing the development of low thermal resistance of 1 mm2 K/W and high compliance and reliability TIMs. These approaches include the use of metal nanosprings (GE), laminated solder and flexible graphite films (Teledyne), multiwalled carbon nanotubes (CNTs) with layered metallic bonding materials (Raytheon), and open-ended CNTs (Georgia Tech (GT)). Following a detailed description of the specific nano-TIM approaches taken and of the metrology developed and used to measure the very low thermal resistivities, the thermal performance achieved by these nano-TIMs, with constant thermal load, as well as under temperature cycling and in extended life testing (aging), will be presented. It has been found that the nano-TIMs developed by all four teams can provide thermal interface resistivities well below 10 mm2 K/W and that GE's copper nanospring TIMs can consistently achieve thermal interface resistances in the range of 1 mm2 K/W. This paper also introduces efforts undertaken for next generation TIMs to reach thermal interface resistance of just 0.1 mm2 K/W.

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The rapid emergence of nanoelectronics, with the consequent rise in transistor density and switching speed, has led to a steep increase in microprocessor chip heat flux and growing concern over the emergence of on-chip hot spots. The application of on-chip high flux cooling techniques is today a primary driver for innovation in the electronics industry. In this paper, the physical phenomena underpinning the most promising on-chip thermal management approaches for hot spot remediation, along with basic modeling equations and typical results are described. Attention is devoted to thermoelectric micro-coolers and two-phase microgap coolers. The advantages and disadvantages of these on-chip cooling solutions for high heat flux hot spots are evaluated and compared.