Improving performance and robustness of domain-specific CPLDs

Holland, M.; Hauck, Scott

doi:10.1145/1117201.1117209

Cited by 2 publications

(2 citation statements)

References 7 publications

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“…In [7] and [10], researchers present a method for automatically generating a transistor level implementation of an FPGA starting from an architectural description of the FPGA with only a 36% area overhead compared to a full-custom implementation and have verified their automated process with the successful fabrication of the resulting FPGA implementation. In [4][5] [6], Holland and Hauck presented an automated tool flow for creating domain-specific PLAs, PALs, and CPLDs. Within this proposed approach, a domain can be loosely defined as a set of similar applications, such as sequential, combinational, floating point, or encryptions domains.…”

Section: Related Workmentioning

confidence: 99%

Design space exploration for application specific FPGAS in system-on-a-chip designs

Hammerquist

Lysecky

2008

2008 IEEE International SOC Conference

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The inclusion of field programmable gate arrays (FPGAs) within a system-on-a-chip (SOC) design offers programmability, flexibility, and reconfigurability not possible with application specific integrated circuits (ASIC) or fullcustom implementations. However, these benefits come at the expense of significant area, performance, and power consumption overheads compared to ASIC or full-custom circuits. As a typical SOC design will require fabrication of the final integrated circuit, rather than rely on a generic FPGA architecture, an FPGA integrated within an SOC design can be optimized for the specific intended application. In this paper, we present an initial design space exploration framework for generating an application specific FPGA (ASFPGA) by tailoring several FPGA architectural features for a specific hardware circuit to improve the area, delay, or energy consumption compared to traditional FPGA designs and reduce the overheads of utilizing an FPGA compared to ASIC and full custom implementations.

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Section: Related Workmentioning

confidence: 99%

Design space exploration for application specific FPGAS in system-on-a-chip designs

Hammerquist

Lysecky

2008

2008 IEEE International SOC Conference

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“…The state of each of these configuration bits is set when the programmable logic core is programmed, usually at power-up. Other logic elements based on multiplexers [31], product terms [104] or arithmetic units [41]- [43] can also be used.…”

Section: ) Hardware Programmabilitymentioning

confidence: 99%

System-on-Chip: Reuse and Integration

et al. 2006

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| Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design.In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.KEYWORDS | Analog intellectual property (IP); intellectual property (IP) cores; network-on-chip (NoC); platform-based design; programmable intellectual property (IP); system-onchip testing; system-on-chip verification; system-on-chip (SoC)

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Improving performance and robustness of domain-specific CPLDs

Cited by 2 publications

References 7 publications

Design space exploration for application specific FPGAS in system-on-a-chip designs

Design space exploration for application specific FPGAS in system-on-a-chip designs

System-on-Chip: Reuse and Integration

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