Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers

Leon, Vasileios; Paparouni, Theodora; Petrongonas, Evangelos; Soudris, Dimitrios; Pekmestzi, Kiamal

doi:10.1145/3448980

Cited by 15 publications

(7 citation statements)

References 35 publications

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“…However, the high bit width and large computation volume brought by floating-point calculations still pose a challenge for onchip deployment. Currently, introducing approximate computing into floating point could significantly enhance energy efficiency [28,29]. Approximate computing can substantially accelerate the speed of operations and reduce the complexity of circuit.…”

Section: Discussionmentioning

confidence: 99%

MDCIM: MRAM-Based Digital Computing-in-Memory Macro for Floating-Point Computation with High Energy Efficiency and Low Area Overhead

Liu,

Tan,

Gan

et al. 2023

Applied Sciences

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Computing-in-Memory (CIM) is a novel computing architecture that enormously improves energy efficiency and reduces computing latency by avoiding frequent data movement between the computation and memory units. Currently, digital CIM is regarded as more suitable for high-precision operations represented in floating-point arithmetic, as it is not limited by the bit width of ADC/DAC in analog CIM. However, the development of DCIM still faces two problems: On the one hand, mainstream SRAM-based DCIM memory cells introduce large area overheads, which contain at least six transistors per cell. On the other hand, existing DCIM solutions can only support the computing precision up to FP32, failing to meet the demands of high-accuracy application scenarios. To overcome these problems, this work designs a novel SOT-MRAM-based digital CIM macro (MDCIM) with higher area/energy efficiency and achieves double-precision floating-point (FP64) computation with a modified fused multiply–accumulate (FMA) module. The proposed design is synthesized with a 55 nm CMOS technology node, achieving 0.62 mW power consumption, 26.9 GOPS/W, and 0.332 GOPS/mm2 energy efficiency at 150 MHz with 1.08 V supply. Circuit level simulation results show that the MDCIM can achieve higher area utilization compared to previous SRAM-based CIM designs.

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Section: Discussionmentioning

confidence: 99%

MDCIM: MRAM-Based Digital Computing-in-Memory Macro for Floating-Point Computation with High Energy Efficiency and Low Area Overhead

Liu,

Tan,

Gan

et al. 2023

Applied Sciences

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“…In the field of approximate circuit design, approximation methods are applied at component level, e.g., adders and multipliers [10][11][12][13][14][15][16][17][18][19], as well as to bigger accelerators [20][21][22][23]. Most of these works focus on logic simplification techniques, namely, aim at reducing the circuit complexity of the designs by pruning circuit nodes or using inexact building blocks.…”

Section: Circuit Approximation Techniquesmentioning

confidence: 99%

Design Space Exploration on High-Order QAM Demodulation Circuits: Algorithms, Arithmetic and Approximation Techniques

et al. 2021

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Every new generation of wireless communication standard aims to improve the overall performance and quality of service (QoS), compared to the previous generations. Increased data rates, numbers and capabilities of connected devices, new applications, and higher data volume transfers are some of the key parameters that are of interest. To satisfy these increased requirements, the synergy between wireless technologies and optical transport will dominate the 5G network topologies. This work focuses on a fundamental digital function in an orthogonal frequency-division multiplexing (OFDM) baseband transceiver architecture and aims at improving the throughput and circuit complexity of this function. Specifically, we consider the high-order QAM demodulation and apply approximation techniques to achieve our goals. We adopt approximate computing as a design strategy to exploit the error resiliency of the QAM function and deliver significant gains in terms of critical performance metrics. Particularly, we take into consideration and explore four demodulation algorithms and develop accurate floating- and fixed-point circuits in VHDL. In addition, we further explore the effects of introducing approximate arithmetic components. For our test case, we consider 64-QAM demodulators, and the results suggest that the most promising design provides bit error rates (BER) ranging from 10−1 to 10−4 for SNR 0–14 dB in terms of accuracy. Targeting a Xilinx Zynq Ultrascale+ ZCU106 (XCZU7EV) FPGA device, the approximate circuits achieve up to 98% reduction in LUT utilization, compared to the accurate floating-point model of the same algorithm, and up to a 122% increase in operating frequency. In terms of power consumption, our most efficient circuit configurations consume 0.6–1.1 W when operating at their maximum clock frequency. Our results show that if the objective is to achieve high accuracy in terms of BER, the prevailing solution is the approximate LLR algorithm configured with fixed-point arithmetic and 8-bit truncation, providing 81% decrease in LUTs and 13% increase in frequency and sustains a throughput of 323 Msamples/s.

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“…At the beginning of the 21st century, the rapid increase in the capacity and design size of FPGAs, the integration of digital signal processing modules, and the rich internal multiplication and accumulation units capable of performing a large number of multiplication and addition operations in convolution [6] . In 2019, Leon et al [7] and Huang et al [8] reduced the parameters of the network model by about six times by using an FPGA platform for YOLO networks. In recent years, better performance has been pursued to accommodate deep learning algorithms.…”

Section: Introductionmentioning

confidence: 99%

Hardware Acceleration Schemes for Convolutional Neural Networks

Xie,

Jiang,

Peng

et al. 2023

J. Phys.: Conf. Ser.

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This paper presents a hardware acceleration design for convolutional neural networks. Floating-point fixed-point operations, pipeline interlayer parallel acceleration, and design space exploration are the three key areas of optimization, and optimized modules can be used to build various networks with convolutions according to specifications for the application scenario, thus achieving a universal design. The experimental results show that the optimization of hardware resources improves the speed and performance of the algorithm, and can withstand larger data volumes and higher real-time requirements. The system achieves an accuracy of 95.09% and an inference speed of 0.237 ms per image, with a high processing speed. As a result, convolutional neural networks may now be used in a wider variety of application scenarios and manage larger datasets and higher real-time demands thanks to the design solutions presented in this research.

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Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers

Cited by 15 publications

References 35 publications

MDCIM: MRAM-Based Digital Computing-in-Memory Macro for Floating-Point Computation with High Energy Efficiency and Low Area Overhead

MDCIM: MRAM-Based Digital Computing-in-Memory Macro for Floating-Point Computation with High Energy Efficiency and Low Area Overhead

Design Space Exploration on High-Order QAM Demodulation Circuits: Algorithms, Arithmetic and Approximation Techniques

Hardware Acceleration Schemes for Convolutional Neural Networks

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