Improving soft-error tolerance of FPGA configuration bits

A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA

“…For the comparisons purposes, we used transistor dimensions similar to given in [9]. Figure 5 shows ASRAM0 cell used in [9].…”

“…We designed three cells to determine and compare Q crit . These three cells are: standard 6-transistor SRAM, asymmetric SRAM (ASRAM0) [9], and our new asymmetric cell RSRAM0 (Refreshing SRAM). Both cells, ASRAM0 and RSRAM0, are hard-0 cells.…”

“…It was observed in [9] that the configuration bit-stream of FPGA contains 87% zeros across different designs. The main reason for higher number of zeros would be due to unused large number of the routing bits.…”

“…Section III describes the design of our new asymmetric cell. In section IV, we analyze the soft error tolerance of our new cell and compare it with standard SRAM cell and asymmetric cell used in [9]. Section V discusses the usage of our cell in the configuration SRAM of FPGAs.…”

“…This cell design was based on using different threshold voltage of the cell transistors. An approach was proposed in [9] to reduce soft errors in the configuration memory of FPGA. Their technique uses asymmetric cell developed in [10].…”