Improving STT-MRAM density through multibit error correction

Bel, Brandon Del; Kim, Jong Yeon; Kim, Chris H.; Sapatnekar, Sachin S.

doi:10.7873/date.2014.195

Cited by 7 publications

(7 citation statements)

References 18 publications

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“…Therefore, it is not possible to meet the reliability target without applying ECC. This result matches the results in [Xu et al, 2009;Del Bel et al, 2014;Pajouhi et al, 2015;Kwon et al, 2015].…”

Section: Resultssupporting

confidence: 92%

“…Nevertheless, they suffer from poor reliability that manifests in the form of low manufacturing yield, as well as run-time errors. Furthermore, ensuring high reliability through design leads to increased read and write energy and reduced density [Wu et al, 2009;Zhou et al, 2009;Xu et al, 2009;Del Bel et al, 2014;Kang et al, 2013;Yang et al, 2012].…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, it enables more efficient read and write operations in STT-MRAM bit-cells, and can result in enhanced yield. Recent research has shown that ECC can be used to improve the density and energy efficiency of STT-MRAMs [Xu et al, 2009;Del Bel et al, 2014;Pajouhi et al 2015;Kwon et al 2015]. These research efforts focus on enhancing reliability; however, they do not distinguish between yield and run-time reliability.…”

Section: Introductionmentioning

confidence: 99%

“…These research efforts focus on enhancing reliability; however, they do not distinguish between yield and run-time reliability. In [Del Bel et al, 2014] the authors consider ECC and address run-time reliability. However, they do not consider the impact of process variations on the run-time reliability and retention time.…”

Section: Introductionmentioning

confidence: 99%

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Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC

Pajouhi

Fong

Raghunathan

et al. 2016

J. Emerg. Technol. Comput. Syst.

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Spin-Transfer Torque MRAMs are attractive due to their non-volatility, high density and zero leakage. However, STT-MRAMs suffer from poor reliability due to shared read and write paths. Additionally, conflicting requirements for data retention and write-ability (both related to the energy barrier height of the storage device) makes design more challenging. Furthermore, the energy barrier height depends on the geometry of the storage. Any variations in the geometry of the storage device lead to variations in the energy barrier height. In order to address poor reliability of STT-MRAMs, usage of Error Correcting Codes (ECC) has been proposed. Unlike traditional CMOS memory technologies, ECC is expected to correct both soft and hard errors in STT-MRAMs. To achieve acceptable yield with low write power, stronger ECC is required, resulting in increased number of encoded bits and degraded memory capacity. In this paper, we propose Failure-aware ECC (FaECC), which masks permanent faults while maintaining the same correction capability for soft errors without increased number of encoded bits. Furthermore, we investigate the impact of process variations on run-time reliability of STT-MRAMs. In order to analyze the effectiveness of our methodology, we developed a cross-layer simulation framework that consists of device, circuit and array level analysis of STT-MRAM memory arrays. Our results show that using FaECC relaxes the requirements on the energy barrier height, which reduces the write energy and results in smaller access transistor size and memory array area.

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Section: Resultssupporting

confidence: 92%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC

Pajouhi

Fong

Raghunathan

et al. 2016

J. Emerg. Technol. Comput. Syst.

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“…Apart from write failures, STT-MRAMs are also subject to read decision failures, where the value stored in a bit-cell is incorrectly sensed due to process variations, and read disturb failures where a read operation inadvertently ends up writing into the bit-cell. These failures are addressed through a range of techniques including device and circuit optimization, manufacturing test and self-repair, and error correcting codes [12], [13], [15], [16]. Apart from write/read failures, memories may also have failures due to thermal noise, which causes stochastic flipping in the bit-cells.…”

Section: Fig 2: Stt-mram Bit-cellmentioning

confidence: 99%

Computing in Memory With Spin-Transfer Torque Magnetic RAM

Jain

Ranjan

Roy

et al. 2018

IEEE Trans. VLSI Syst.

291

187

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Abstract-In-memory computing is a promising approach to addressing the processor-memory data transfer bottleneck in computing systems. We propose Spin-Transfer Torque Computein-Memory (STT-CiM), a design for in-memory computing with Spin-Transfer Torque Magnetic RAM (STT-MRAM). The unique properties of spintronic memory allow multiple wordlines within an array to be simultaneously enabled, opening up the possibility of directly sensing functions of the values stored in multiple rows using a single access. We propose modifications to STT-MRAM peripheral circuits that leverage this principle to perform logic, arithmetic and complex vector operations. We address the challenge of reliable in-memory computing under process variations by extending ECC schemes to detect and correct errors that occur during CiM operations. We also address the question of how STT-CiM should be integrated within a generalpurpose computing system. To this end, we propose architectural enhancements to processor instruction sets and on-chip buses that enable STT-CiM to be utilized as a scratchpad memory. Finally, we present data mapping techniques to increase the effectiveness of STT-CiM. We evaluate STT-CiM using a device-to-architecture modeling framework, and integrate cycle-accurate models of STT-CiM with a commercial processor and on-chip bus (Nios II and Avalon from Intel). Our system-level evaluation shows that STT-CiM provides system-level performance improvements of 3.93x on average (upto 10.4x), and concurrently reduces memory system energy by 3.83x on average (upto 12.4x).

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Method for ex‐situ training in memristor‐based neuromorphic circuit using robust weight programming method

2015

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A feedback-based weight programming method for a high-density crossbar without the use of any transistor or diode isolation is presented. A series of reads is applied to the crossbar before each write that is able to determine the resistance of each memristor in the crossbar despite the many parallel resistance paths. This is essential because the variation observed in memristor crossbars makes programming very difficult when using just a single write pulse and no error checking. A neuromorphic circuit is programmed using this method. Results show successful ex-situ training of a high-density crossbar with significant area savings when compared with a one transistor one memristor design.Introduction: Memristor crossbars [1-3] can perform many tasks including multi-bit storage, logic function programming and neuromorphic learning. Crossbars provide low energy, high throughput (parallel computations) and a low area compute structure. It has previously been shown that memristor crossbars can be more than 300 000 times more energy efficient than a commercial Xeon processor when processing large neural network applications [4].For the crossbar to perform a specific function, the resistance level of the individual memristor needs to be set to specific values. In many cases this will require fine tuning across a large range of resistance values. Memristor crossbars are prone to device variations [3], and when a voltage pulse is applied to a memristor the amount of resistance change that occurs is somewhat stochastic. Therefore, this fine tuning would likely be a feedback process where each resistance is repetitively sensed and updated until the desired resistance is obtained [5]. Owing to the parallel nature of the memristor crossbar, a single read pulse cannot be used to determine a single memristor resistance state. However, this Letter shows how N read pulses can be used to determine all memristor resistances within a crossbar containing N × M memristors.This Letter presents an approach to update the states without having isolation devices in the crossbar. This will enable lower area, more compact crossbars. Alternatively, a transistor can be added at each crosspoint to allow reading each individual device. However, a memristor crossbar is able to represent synaptic weights with a greater density than that of the brain tissue [1], and decreasing this density by adding extra transistors should be avoided. As another alternative, virtual ground opamps could be placed on each crossbar column [6], but this is an expensive approach in terms of area and energy [2].Given the complexity of this programming method, it will be most beneficial for systems where fewer writes are performed such as readonly memory, programmable logic and especially the ex-situ training of neuromorphic circuits. Training a large crossbar using a neuromorphic learning algorithm can be very time consuming. Determining the desired set of resistance values externally would be beneficial so that each individual crossbar will not require a lengthy in-sit...

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Improving STT-MRAM density through multibit error correction

Cited by 7 publications

References 18 publications

Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC

Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC

Computing in Memory With Spin-Transfer Torque Magnetic RAM

Method for ex‐situ training in memristor‐based neuromorphic circuit using robust weight programming method

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