Improving the Endurance Characteristics Through Boron Implant at Active Edge in 1 G NAND Flash

Abstract

One of the most important issues of NAND flash memory is reliability problems caused by oxide and interface traps. But it has been revealed that their generation rate increases by FolwerNordheim current stressing on the tunnel oxide as the channel width of shallow trench isolation (STI) isolated NAND flash cells shrinks and electric field is increased at active edge of STI profile. By adjusting the boron doping of active edge, we decrease not only the electric field but also the trap generation. Also we confirmed the improvement of endurance and bake retention characteristics.

Nitride engineering and the effect of interfaces on Charge Trap Flash performance and reliability

“…Though there is a strong dependence on the position of the SiON interface layer, the erase state V FB shows negligible degradation for Si + /N + = 4/4 and 6/2 (nm) bi-layer device. This is in stark contrast to the single layer nitride endurance results in this study as well as in the literature [3], [6], [7], [16], [17] and consistent with recent results on NAN stacks [8] cycling endurance is worth a mention as the improvement is inexplicable by attribution to simply the ratio of Si + vs. N + nitride layer thickness in the bi-layer stack (as plausible in the case of W/E or retention performance). The signature effect of the SiON barrier layer explains the improvement for the bi-layer endurance as single layer nitride endurance is poor -regardless of the choice of nitride composition.…”