Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration

Ichinomiya, Yoshihiro; Tanoue, Shiro; Amagasaki, Motoki; Iida, Masahiro; Kuga, Morihiro; Sueyoshi, Toshinori

doi:10.1109/fccm.2010.16

Cited by 46 publications

(12 citation statements)

References 5 publications

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“…In particular, a module suffering from permanent single event upsets (SEU) is recovered by reconfiguring it with a correct copy. DPR has been used in such fault-tolerant applications (e.g., [Paulsson et al 2006;Ichinomiya et al 2010;Cetin et al 2013]), and this case study aims to apply ReSim and coverage analysis to verifying the DPR activities in fault-tolerant applications. We also compared the results of coveragedriven verification with ad-hoc on-chip debugging.…”

Section: Case Study Ii: In-house Fault-tolerant Applicationmentioning

confidence: 99%

Simulation-based functional verification of dynamically reconfigurable systems

Gong

Diessel

2014

ACM Trans. Embed. Comput. Syst.

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Dynamically reconfigurable systems (DRS) implemented using field-programmable gate arrays (FPGAs) allow hardware logic to be partially reconfigured while the rest of the design continues to operate. By mapping multiple reconfigurable hardware modules to the same physical region of an FPGA, such systems are able to time-multiplex their modules at runtime and adapt themselves to changing execution requirements. This architectural flexibility introduces challenges for verifying system functionality. New simulation approaches are required to extend traditional simulation techniques to assist designers in testing and debugging the time-varying behavior of DRS. This article summarizes our previous work on ReSim, the first tool to allow cycle-accurate yet physically independent simulation of a DRS reconfiguring both its logic and state. Furthermore, ReSim-based simulation does not require changing the design for simulation purposes and thereby verifies the implementation-ready design instead of a variation of the design. We discuss the conflicting requirements of simulation accuracy and verification productivity in verifying DRS designs and describe our approach to resolve this challenge. Through a range of case studies, we demonstrate that ReSim assists designers in detecting fabric-independent bugs of DRS designs and helps to achieve verification closure of DRS design projects. ACM Reference Format:Lingkan Gong and Oliver Diessel. 2014. Simulation-based functional verification of dynamically reconfigurable systems.

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Section: Case Study Ii: In-house Fault-tolerant Applicationmentioning

confidence: 99%

Simulation-based functional verification of dynamically reconfigurable systems

Gong

Diessel

2014

ACM Trans. Embed. Comput. Syst.

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“…A more coarse granularity can be achieved if the triplication and voting are applied through the device on a basis of bigger modules and their respective outputs. An example of this approach is shown in [1] where a complete microcontroller was triplicated and the voting was applied on its bus signals. Depending on the size of the triplicated modules, the characteristics of the TMR implementation change accordingly.…”

Section: Related Workmentioning

confidence: 99%

“…This approach has been used in many studies, e.g. [1] and [2], especially for SRAM based FPGAs aimed at improving the overall system reliability of these so-called Commercial-Off-The-Shelf (COTS) devices. In contrast to device shielding, TMR relies on redundancies in the design to avoid wrong outputs, instead of preventing the SEUs from occurring at all.…”

Section: Introductionmentioning

confidence: 99%

Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA

Kretzschmar

Astarloa

Lázaro

et al. 2012

2012 International Conference on Reconfigurable Computing and FPGAs

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Triple Module Redundancy (TMR) is a popular technique for protecting critical FPGA designs. Although automatic tools for TMR generation mostly use triplication on flip-flop level, designers may opt for different approaches. This work analyses the impact of different granularities on TMR architectures based on a coarse-and a medium-grained TMR implementation of a shared Wishbone interconnection. The actual robustness of these different implementations is measured on a Xilinx Virtex-5 FPGA by using error injection into the configuration bitstream. A specialized test setup comprising two FPGAs boards is introduced so as to allow for the execution of the robustness testing. Based on the coarse-grained architecture, a fine categorization of errors in TMR architectures can be obtained.

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“…This technique is very popular in aerospace applications, where the SEEs have an extended presence and the failure cost is extremely high [5] [6] and it is also used in processor systems hardening approaches [7] [8]. Once the element is tripled the final output is determined by a majority voting.…”

Section: Introduction and Related Workmentioning

confidence: 98%

Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

Gomez-Cornejo

Zuloaga

Kretzschmar

et al. 2013

IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society

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This paper presents a new approach of the lockstep technique to protect FPGA designs with soft core processors against Single Event Upsets (SEUs) and Single-Event Transients (SETs). One of the biggest drawbacks when using the lockstep technique is the processor context saving and restoring latency. Our approach minimizes the latency thanks to a specific architecture and a specifically adapted 8-bit soft core processor. The proposed architecture is also hardened by using ECC code in memory elements. In this way, this approach combines the benefits of fast SEUs detection with fast restoration of the device functionality. This is demonstrated by running a serial communication application hardened with the new lockstep approach and comparing the results with a Triple Modular Redundancy (TMR) implementation. The design has been implemented in a Xilinx Virtex-5 FPGA.

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Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration

Cited by 46 publications

References 5 publications

Simulation-based functional verification of dynamically reconfigurable systems

Simulation-based functional verification of dynamically reconfigurable systems

Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA

Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor

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