In-depth overlay contribution analysis of a poly-layer reticle

Abstract

Wafer overlay is one of the key challenges for lithography in semiconductor device manufacturing, this becomes increasingly challenging following the shrinking of the device node. Some of Low k1 techniques, such as Double Exposure add additional burden to the overlay margin because on most critical layers the pattern is created based on exposures of 2 critical masks. Besides impact on overlay performance, any displacement between those two exposures leads to a significant impact on space CD uniformity performance as well. Mask registration is considered a major contributor to within-field wafer overlay.We investigated in-die registration performance on a critical poly-layer reticle in-depth, applying adaptive metrology rules, We used Thin-Plate-Splinefit (TPS) and Fourier analysis techniques for data analysis. Several systematic error components were observed, demonstrating the value of higher sampling to control mask registration performance

In-die mask registration for multi-patterning

“…This very tight specification requires significantly better control of the e-beam mask writer. In the past, the principle registration metric, measurement repeatability, simply followed the ITRS from technology node to technology node, but previously presented papers [2] show some hints that mask lithography systems may have inherent placement errors which are not captured by standard OQC (outgoing quality check). Other evaluations have demonstrated, at least on test masks, that registration errors transfer to the wafer [3].…”