In depth static and low-frequency noise characterization of n-channel FinFETs on SOI substrates at cryogenic temperature

Achour, H.; Cretu, Bogdan; Routoure, Jean‐Marc; Carin, R.; Talmat, Rachida; Benfdila, A.; Simoen, Eddy; Claeys, Cor

doi:10.1016/j.sse.2014.04.001

Cited by 13 publications

(19 citation statements)

References 33 publications

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“…At different temperatures, noise measurements as a function of the applied gate voltage were performed, as in [10]. This permits to put in evidence, for a fixed temperature operation, Lorentzian contributions which can be assigned to traps located in the depleted fins.…”

Section: Experimental Methodologymentioning

confidence: 99%

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Identification of Si film traps in p-channel SOI FinFETs using low temperature noise spectroscopy

Achour

Cretu

Simoen

et al. 2015

Solid-State Electronics

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Section: Experimental Methodologymentioning

confidence: 99%

“…The evolution of the low frequency noise with the applied gate voltage at different temperatures was already studied for pchannel standard and strained SOI FinFETs with the aim to investigate the quality of the gate oxide interface through the 1/f noise analysis [10].…”

Section: Introductionmentioning

confidence: 99%

Identification of Si film traps in p-channel SOI FinFETs using low temperature noise spectroscopy

Achour

Cretu

Simoen

et al. 2015

Solid-State Electronics

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“…gives accurate values for the parameters A 0i and f 0i of the i=1,j Lorentzians in the spectrum [11,12].…”

Section: Principle Of Gr Noise and Rts Spectroscopymentioning

confidence: 96%

“…Measuring the f 0i values at different sample temperatures enables to construct an Arrhenius law like in Fig. 2 [11,12]:…”

Section: Principle Of Gr Noise and Rts Spectroscopymentioning

confidence: 99%

Low-Frequency Noise Spectroscopy of Bulk and Border Traps in Nanoscale Devices

Simoen¹,

Cretu

Wen³

et al. 2015

SSP

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The principles and application of Generation-Recombination (GR) noise spectroscopy will be outlined and illustrated for the case of traps in Ultra-Thin Buried Oxide Silicon-on-Insulator nMOSFETs and for vertical polycrystalline silicon nMOSFETs. It will be shown that for scaled devices the GR noise is originating from a single defect, giving rise to a so-called Random Telegraph Signal (RTS). Several methods will be described for an accurate extraction of the RTS parameters (amplitude, up and down time constant). It will be demonstrated that besides the deep-level parameters also the position of the trap in the channel can be derived from a numerical modeling of the RTS amplitude.

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“…Um dos efeitos da separação do vale de energia da banda de condução ∆ 6 nos vales ∆ 2 e ∆ 4 , partindo do silício sem tensionamento mecânico para o silício tensionado tensivamente, é a supressão do espalhamento de fônons entre os vales ∆ 2 e ∆ 4 , responsável por menor γ em transistores sSOI em comparação com SOI (KOYAMA et al, 2013;TAKAGI et al, 1996). (ACHOUR et al, 2014). Para NW SGOI estreito, DIBL estabiliza próximo de 2mV/V para T ≤ 100K, indicando excelente imunidade ao efeito do aumento de V DS em V TH , conforme esperado para NWs de canal longo (L = 10µm).…”

Section: T = 300kunclassified

Avaliação da influência da evolução das tecnologias de fabricação de nanofios transistores MOS sobre suas características elétricas

Paz¹

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This work aims to study the influence of different fabrication technologies of inversion mode nanowires MOS transistors (NWs) through the evaluation and comparison of their electrical characteristics obtained from experimental measurements. Tridimensional numerical simulations are also used to allow the understanding of observed physical effects and to validate parameters extraction methods proposed in this work. Following the technological evolution of fabrication of NWs recently proposed, the influence of fin width, strain and stacking of nanowires is verified, mainly, over analog behavior and carriers' mobility. The comparisons performed in this work allow picking the technology that presents the best performance for each parameter analyzed. Several nanowires with fin width as narrow as 9.5nm and up to 10µm (quasi-planar) are analyzed. The fin width influence on the analog parameters is studied for n-and p-type non-stacked NWs with channel lengths of 10µm and 40nm. Effective mobility results are correlated to the harmonic distortion to explain linearity peaks behavior with temperature and fin width. Narrow transistors show improved linearity mainly due to higher intrinsic voltage gain. Back bias influence is studied in narrow NWs, where mobility varies due to carriers' density and inversion channel position along the fin. Strained and unstrained n-type NWs are compared using experimental results in the temperature range of 300 down to 10K, where mobility behavior is the major responsible for the analog parameters dependence on temperature. Uniaxial compressive strain obtained through SiGe in p-type nanowires shows to be beneficial for mobility, where improvements reach up to 68% for fin width of 20nm at room temperature. Strained vertically stacked p-type SOI nanowires with inner spacers and [110]-and [100]-oriented channels are studied as a function of both fin width and channel length. Procedures to extract the effective oxide thickness and fin width are adapted and validated through tridimensional numerical simulations. Overall effective mobility for stacked NWs is lower in comparison to nonstacked NWs due to small contribution from the top GAA level and threshold voltage mismatches, according to the investigation promoted by the proposed methodology to dissociate the low field mobility contributions from the top and bottom levels that compose the stacked structure.

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In depth static and low-frequency noise characterization of n-channel FinFETs on SOI substrates at cryogenic temperature

Abstract: HAL is a multidisciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers.

Cited by 13 publications

References 33 publications

Identification of Si film traps in p-channel SOI FinFETs using low temperature noise spectroscopy

Identification of Si film traps in p-channel SOI FinFETs using low temperature noise spectroscopy

Low-Frequency Noise Spectroscopy of Bulk and Border Traps in Nanoscale Devices

Avaliação da influência da evolução das tecnologias de fabricação de nanofios transistores MOS sobre suas características elétricas

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