In-die photomask registration and overlay metrology with PROVE using 2D correlation methods

Seidel, Dirk; Arnz, M.; Beyer, Dirk

doi:10.1117/12.896592

Cited by 6 publications

(6 citation statements)

References 12 publications

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“…The metrology performance is guaranteed since a short detection wavelength (193-nm) and a high NA in combination with litho-grade optics is used. Moreover, the unique stage concept in combination with tight environmental control enables absolute and accurate registration measurements as was demonstrated before [3,4]. In Figure 3 we schematically show how the mask registration measurements on the PROVE  tool are performed.…”

Section: Stack and Off-line Mask Registration Measurementsmentioning

confidence: 99%

“…The test mask we use throughout this work is based on a (Litho-Etch) 3 process flow that defines the Metal 1 layer for a 7-nm node technology flow. The final Metal 1 device layer is reconstructed out of three sub-layers: M1A, M1B, and M1C.…”

Section: Mask Layoutmentioning

confidence: 99%

“…The problems mentioned above regarding the wafer metrology are basically non-existing when we characterize the placement errors on the PROVE  mask registration tool from Zeiss [3,4]. One big difference is of course that the measurements can be done at mask level (4×) instead of wafer level (1×).…”

Section: Stack and Off-line Mask Registration Measurementsmentioning

confidence: 99%

“…The sampling area of the PROVE  tool can be increased by making use of the Local Registration Map (LRM) functionality [3,4]. This LRM functionality enabled us to probe much larger areas comparable to what on-wafer metrology tools do.…”

Section: Introductionmentioning

confidence: 99%

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Direct correlation between mask registration and on-wafer measurements for individual logic device features

Haren

Steinert

Mouraille

et al. 2022

Photomask Technology 2022

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In all investigations that we performed over the past years; it has been clearly demonstrated that the off-line mask-to-mask overlay as determined on the Zeiss PROVE  tool correlates very well with the on-wafer measurements. It all started off with a correlation study utilizing wafer alignment marks. Wafer alignment marks are metrology structures that can be read out inside ASML scanners by the wafer alignment sensor. In that work, the impact of the reticle alignment marks required to align the mask inside the scanner was incorporated as well. An excellent correlation (R 2 > 0.96) was shown with an accuracy of 0.58-nm. This result was achieved after carefully setting up an experiment in photoresist and by ruling out any other additional overlay contributors other than mask and the scanner baseline overlay performance.After this initial success, we continued the investigation by considering µ-DBO (Diffraction Based Overlay) metrology targets that can be read out on an ASML Yieldstar (YS:375) overlay metrology tool. In this work, the complexity of the experiment was increased. Instead of using only photo resist, an industry relevant process Litho-Etch process flow was selected. The mask was written on a state-of-the-art writing tool (EBM-9000). Again, excellent correlation coefficients (R 2 > 0.92) were obtained. This time within the sub-nanometer range at wafer level.During the execution of that work, an error source that contributes to the small mismatch (< 0.14-nm) between mask and on-wafer measurements was addressed: the sampling scheme difference of the signal generating areas. While the PROVE  tool has been designed to measure local (feature) placement errors, this is not the case for an overlay metrology tool or the scanner wafer alignment sensor. For the latter two metrology systems, a position is obtained from a much larger region of interest (ROI) for which local placement errors are averaged out. The observed mismatch can easily be mitigated by increasing the number of PROVE  measurements with a small ROI to match it with the ROI of the overlay metrology tool or the wafer alignment sensor.While studying the increasing number of local registration measurements by the PROVE  tool, an interesting observation was made. The way the mask had been written on the mask e-beam writer seemed to be reflected in the residual local registration measurements! Stripes were observed that appear to be running across the full width of the mask. Since the typical dimensions of the stripes at wafer level are small compared to the areas that are used for overlay measurements and/or wafer alignment measurements, they are hard to detect on wafer by using optical techniques.In this follow-up work, we explore the correlation between mask registration measurements and the on-wafer measurement for individual device features. This means that we make another step-in complexity, the length scales of interest are now significantly below the typical dimensions of an overlay metrology target. To continue the correlation study, a larg...

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Section: Stack and Off-line Mask Registration Measurementsmentioning

confidence: 99%

Section: Mask Layoutmentioning

confidence: 99%

Section: Stack and Off-line Mask Registration Measurementsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Direct correlation between mask registration and on-wafer measurements for individual logic device features

Haren

Steinert

Mouraille

et al. 2022

Photomask Technology 2022

View full text Add to dashboard Cite

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“…Hence, there remain to ways to improve overlay metrology: Stick with IBO but improve the mark layout, or adjust the measurement scheme and move to diffraction-based overlay metrology (DBO). In order to motivate our looking beyond IBO, we note that also in mask registration limitations of image-and threshold-based metrology have been encountered and solutions beyond these methods are being investigated or even commercially available [2], [3] .…”

Section: What Can We Do To Improve Overlay Metrology?mentioning

confidence: 99%

Overlay metrology for low-k<sub>1</sub>: challenges and solutions

Neumann

Lee²,

Yang³

et al. 2012

SPIE Proceedings

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Typical overlay metrology marks like Box-in-Box or Advanced-Imaging-Marks print surprisingly poor when exposed with extreme off-axis-illumination. This paper analyzes the root-cause for this behavior and establishes a method how to understand and predict the results of overlay metrology on resist. A simulation flow is presented which covers the lithographic exposure as well as the actual inspection of the resist profiles. This flow is then used to study the impact of scanner/process imperfections on the overlay measurements; both image-based and diffraction-based overlay metrology are covered. This helps to gain a deeper understanding of the critical parameters in the printing and inspection of overlay marks, and eventually develop and assess mark enhancement strategies for image-based overlay metrology such as chopping, or assess the benefit of diffraction-based overlay metrology. In parallel to the simulations, results of wafer exposures are presented which investigate various aspects of overlay metrology and validate our simulations.

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