In-plane mobility anisotropy and universality under uni-axial strains in n- and p-MOS inversion layers on [100], [110], and [111] Si

Irie, Hiroshi; Kita, Koji; Kyuno, Kentaro; Toriumi, Akira

doi:10.1109/iedm.2004.1419115

Cited by 114 publications

(110 citation statements)

References 5 publications

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“…1 the simulated zero magnetic field mobilities of unstrained Si bulk pMOS transistors are shown, which reproduce the measurements from [5] for (100) and [6] for (110) surface orientations very well. The effective mass (Fig.…”

Section: Resultssupporting

confidence: 67%

Simulation of Magnetotransport in Hole Inversion Layers Based on Full Subbands

Pham

Jungemann

Meinerzhagen

Simulation of Semiconductor Processes and Devices 2007

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Magnetotransport of holes in Si inversion layers of 1D MOS capacitors on arbitrarily oriented substrates is simulated. The 6 × 6 k · p Schrödinger equation is solved self-consistently with the confining electrostatic potential to calculate the 2D hole gas subband structure. The transport of holes within the channel is investigated by solving the stationary Boltzmann equation (BTE) for a small lateral driving electric field. The distribution function is either expressed as a polynomial of the magnetic field or expanded into harmonics of the polar angle within 2D k-space (Fourier expansion). The Hall factor and the second order magnetotransport coefficients are calculated. The approximation of the second order coefficient by the square of the channel mobility is shown to fail.

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Section: Resultssupporting

confidence: 67%

Simulation of Magnetotransport in Hole Inversion Layers Based on Full Subbands

Pham

Jungemann

Meinerzhagen

Simulation of Semiconductor Processes and Devices 2007

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“…Then, we convert the stress to mobility variation with piezo-resistive model. Since mobility variation due to stress depends on not only applied stress strength but also orientation between TSV and transistor channel [12], we use the modified piezo-resistive model in equation 12. Here, Π is the tensor of piezo-resistive coefficients for holes and electrons [13], O f (θ) is an orientation factor which is obtained from empirical data in [12] and θ is the degree between center of TSV and transistor channel.…”

Section: Buffer Variation Modeling Under Tsv Induced Stressmentioning

confidence: 99%

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs

Yang

Pak

Zhao

et al. 2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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ABSTRACT3D integration has new manufacturing and design challenges such as timing corner mismatch between tiers and device variation due to Through Silicon Via (TSV) induced stress. Timing corner mismatch between tiers is caused because each tier is manufactured in independent process. Therefore, inter-die variation should be considered to analyze and optimize for paths spreading over several tiers. TSV induced stress is another challenge in 3D Clock Tree Synthesis (CTS). Mobility variation of a clock buffer due to stress from TSV can cause unexpected skew which degrades overall chip performance. In this paper, we propose clock tree design methodology with the following objectives: (a) to minimize clock period variation by assigning optimal zlocation of clock buffers with an Integer Linear Program (ILP) formulation, (b) to prevent unwanted skew induced by the stress. In the results, we show that our clock buffer tier assignment reduces clock period variation up to 34.2%, and the most of stress-induced skew can be removed by our stress-aware CTS. Overall, we show that performance gain can be up to 5.7% with our robust 3D CTS.

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“…Under the bending, the electron mobility degraded more than the hole mobility, because of the difference in the change of the energy band diagram due to the different shape of the conduction band and the valence band. [10] (a) (b) Figure 7 (a) Photo of fixing the devices on a cylinder for the bending test, and (b) Normalized field effect mobilities as a function of the bending diameter To reduce the mechanical stress to the device layer, another polyimide layer was added on top of the device layer. As illustrated in Figure 8, after the single-grain Si TFTs fabrication from spin-coated liquid-Si, a polyimide layer with the thickness of 10 µm was spin-coated on top of the devices.…”

Section: Substrate Transfer Processmentioning

confidence: 99%

(Invited) Single-Grain Si Tfts Fabricated on a Precursor from Doctor-Blade Coated Liquid-Si

et al. 2014

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Printing is attractive for manufacturing flexible circuits. This manuscript presents our investigation of single-grain Si TFTs fabricated from printed liquid-Si, on a polyimide substrate with the maximum process temperature of 350 °C. The field-effect mobility is 460 cm2/Vs for electrons and 121 cm2/Vs for the holes. CMOS inverters were also fabricated. The devices function at the bending diameter of 3 mm. The device performance under the bending stress was discussed.

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In-plane mobility anisotropy and universality under uni-axial strains in n- and p-MOS inversion layers on [100], [110], and [111] Si

Cited by 114 publications

References 5 publications

Simulation of Magnetotransport in Hole Inversion Layers Based on Full Subbands

Simulation of Magnetotransport in Hole Inversion Layers Based on Full Subbands

Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs

(Invited) Single-Grain Si Tfts Fabricated on a Precursor from Doctor-Blade Coated Liquid-Si

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