In the Classroom

Wang, Laung-Terng; Wu, Cheng-Wen; Wen, Xiaoqing

doi:10.1016/b978-012370597-6/50001-9

Cited by 9 publications

(10 citation statements)

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“…Many techniques have been proposed to resolve them. One approach called X-blocking is to eliminate the sources of X-bits by interrupting the normal behavior of the circuit [25]. It is not applicable for trace-based debug that targets on the bugs occurring in the CUD's normal operation.…”

Section: Preliminaries and Motivationmentioning

confidence: 99%

On efficient silicon debug with flexible trace interconnection fabric

Liu

2012

2012 IEEE International Test Conference

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Trace-based debug solutions facilitate to eliminate bugs escaped from pre-silicon verification and have gained wide acceptance in the industry. Generally speaking, a number of "key" signals in the circuit are tapped, but not all of them can be observed at the same time due to the limited trace bandwidth. Therefore, a trace interconnection fabric is utilized to output either a subset of signals with multiplexor (MUX) network or compressed signatures with XOR network to the trace memory/port in each debug run. However, both kinds of trace interconnection fabrics have limitations. On one hand, with MUX-based fabric, the visibility of the circuit is limited and it requires many debug runs to locate errors. On the other hand, with XOR-based fabric, typically clean "golden vectors" (i.e, without unknown bits) are required so that signatures are not corrupted. In this paper, we propose a flexible trace interconnection fabric design that is able to overcome the above limitations, at the cost of little extra design-for-debug hardware. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique.

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Section: Preliminaries and Motivationmentioning

confidence: 99%

On efficient silicon debug with flexible trace interconnection fabric

Liu

2012

2012 IEEE International Test Conference

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“…To avoid yield loss in memory chips, spare elements, i.e., redundant columns, rows, words or small blocks are added to repair faulty storage cells for almost all memories with relatively high capacity [50]. In MBISR, failure bitmap information obtained through test is stored on-chip for repair purpose.…”

Section: A Defect Tolerance In Memory and Vlsi Array Processorsmentioning

confidence: 99%

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Zhang

Han

et al. 2009

IEEE Trans. VLSI Syst.

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Abstract-Homogeneous manycore systems are emerging for tera-scale computation and typically utilize Network-on-Chip (NoC) as the communication scheme between embedded cores. Effective defect tolerance techniques are essential to improve the yield of such complex integrated circuits. We propose to achieve fault tolerance by employing redundancy at the core-level instead of at the microarchitecture level. When faulty cores exist on-chip in this architecture, however, the physical topologies of various manufactured chips can be significantly different. How to reconfigure the system with the most effective NoC topology is a relevant research problem. In this paper, we first show that this problem is an instance of a well known NP-complete problem. We then present novel solutions for the above problem, which not only maximize the performance of the on-chip communication scheme, but also provide a unified topology to Operating System and application software running on the processor. Experimental results show the effectiveness of the proposed techniques.

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“…The reduction in feature size increases the probability that a manufacturing defect in the IC will result in a faulty chip [2]. A very small defect can easily result in a faulty transistor or interconnecting wire when the feature size is less than 100 nm.…”

Section: Introductionmentioning

confidence: 99%